forked from OSchip/llvm-project
200 lines
9.1 KiB
LLVM
200 lines
9.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; CHECK-LABEL: {{^}}fmuladd_f32:
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; CHECK: v_mac_f32_e32 {{v[0-9]+, v[0-9]+, v[0-9]+}}
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define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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float addrspace(1)* %in2, float addrspace(1)* %in3) {
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%r0 = load float, float addrspace(1)* %in1
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%r1 = load float, float addrspace(1)* %in2
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%r2 = load float, float addrspace(1)* %in3
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%r3 = tail call float @llvm.fmuladd.f32(float %r0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_f64:
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; CHECK: v_fma_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2, double addrspace(1)* %in3) {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = load double, double addrspace(1)* %in3
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%r3 = tail call double @llvm.fmuladd.f64(double %r0, double %r1, double %r2)
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store double %r3, double addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_2.0_a_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_a_2.0_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fadd_a_a_b_f32:
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fadd_a_a_b_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r0 = load volatile float, float addrspace(1)* %gep.0
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%r1 = load volatile float, float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %add.0, %r1
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store float %add.1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fadd_b_a_a_f32:
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fadd_b_a_a_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r0 = load volatile float, float addrspace(1)* %gep.0
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%r1 = load volatile float, float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %r1, %add.0
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store float %add.1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_neg_2.0_a_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_neg_2.0_neg_a_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_2.0_neg_a_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]]
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; CHECK: buffer_store_dword [[R2]]
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define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: {{^}}fmuladd_2.0_a_neg_b_f32
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; CHECK-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]]
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; CHECK: buffer_store_dword [[RESULT]]
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define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
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%r1 = load volatile float, float addrspace(1)* %gep.0
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%r2 = load volatile float, float addrspace(1)* %gep.1
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%r2.fneg = fsub float -0.000000e+00, %r2
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2.fneg)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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