forked from OSchip/llvm-project
158 lines
4.1 KiB
ArmAsm
158 lines
4.1 KiB
ArmAsm
// REQUIRES: arm
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// RUN: llvm-mc --triple=thumbv7m-none-eabi --arm-add-build-attributes -filetype=obj -o %t.o %s
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// RUN: echo "SECTIONS { \
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// RUN: .rodata.low 0x8012 : { *(.rodata.low) } \
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// RUN: .text.low 0x8f00 : { *(.text.low) } \
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// RUN: .text.neg 0x9000 : { *(.text.neg) } \
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// RUN: .text.pos 0x10000 : { *(.text.pos) } \
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// RUN: .text.high 0x10100 : { *(.text.high) } \
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// RUN: .data_high 0x1100f : { *(.data.high) } \
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// RUN: } " > %t.script
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// RUN: ld.lld --script %t.script %t.o -o %t
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// RUN: llvm-readobj --symbols %t | FileCheck %s --check-prefix=SYMS
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=thumbv7m-none-eabi %t
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// RUN: llvm-objdump -d --no-show-raw-insn --triple=thumbv7m-none-eabi %t | FileCheck %s
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/// Test the various legal cases for the R_ARM_THM_ALU_PREL_11_0 relocation
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/// Interesting things to note
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/// Range is +- 4095 bytes
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/// The expression is S + A - Pa where Pa is AlignDown(PC, 4) so we will use
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/// 2-byte nops to make some of the adr psuedo instructions 2-byte aligned.
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.section .rodata.low, "a", %progbits
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dat1:
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.byte 0
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dat2:
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.byte 1
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dat3:
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.byte 2
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dat4:
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.byte 3
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.section .text.low, "ax", %progbits
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.balign 4
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.global target1
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.type target1, %function
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target1:
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bx lr
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.type target2, %function
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target2:
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bx lr
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.section .text.neg, "ax", %progbits
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.balign 4
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.global _start
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.thumb_func
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_start:
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nop
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adr.w r0, dat1
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adr.w r1, dat2
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nop
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adr.w r2, dat3
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adr.w r3, dat4
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.balign 4
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adr.w r0, target1
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nop
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adr.w r1, target2
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.section .text.pos, "ax", %progbits
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.balign 4
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.global pos
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.thumb_func
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pos:
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adr.w r2, target3
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nop
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adr.w r3, target4
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.balign 4
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adr.w r0, dat5
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adr.w r1, dat6
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nop
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adr.w r2, dat7
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adr.w r3, dat8
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/// positive addend in instruction, all others are -4 (PC bias)
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adr.w r4, dat5 + 8
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.section .text.high, "ax", %progbits
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.balign 4
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.thumb_func
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.global target3
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target3:
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bx lr
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.thumb_func
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target4:
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bx lr
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.section .data.high, "aw", %progbits
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dat5:
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.byte 0
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dat6:
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.byte 1
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dat7:
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.byte 2
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dat8:
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.byte 3
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// SYMS: Name: dat1
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// SYMS-NEXT: Value: 0x8012
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// SYMS: Name: dat2
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// SYMS-NEXT: Value: 0x8013
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// SYMS: Name: dat3
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// SYMS-NEXT: Value: 0x8014
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// SYMS: Name: dat4
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// SYMS-NEXT: Value: 0x8015
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// CHECK: 00008f00 <target1>:
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// CHECK-NEXT: 8f00: bx lr
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// CHECK: 00008f02 <target2>:
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// CHECK-NEXT: 8f02: bx lr
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// CHECK: 00009000 <_start>:
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// CHECK-NEXT: 9000: nop
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/// AlignDown(0x9002+4, 4) - 0xff2 = 0x8012
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// CHECK-NEXT: 9002: adr.w r0, #-4082
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/// AlignDown(0x9006+4, 4) - 0xff5 = 0x8013
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// CHECK-NEXT: 9006: adr.w r1, #-4085
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// CHECK-NEXT: 900a: nop
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/// AlignDown(0x900c+4, 4) - 0xffc = 0x8014
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// CHECK-NEXT: 900c: adr.w r2, #-4092
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/// AlignDown(0x9010+4, 4) - 0xfff = 0x8015
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// CHECK-NEXT: 9010: adr.w r3, #-4095
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/// AlignDown(0x9014+4, 4) - 0x117 = 0x8f01
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// CHECK-NEXT: 9014: adr.w r0, #-279
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// CHECK-NEXT: 9018: nop
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/// AlignDown(0x901a+4, 4) - 0x119 = 0x8f03
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// CHECK-NEXT: 901a: adr.w r1, #-281
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// CHECK: 00010000 <pos>:
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/// AlignDown(0x10000+4, 4) + 0xfd = 0x10101
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// CHECK-NEXT: 10000: adr.w r2, #253
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// CHECK-NEXT: 10004: nop
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/// AlignDown(0x10006+4, 4) + 0xfb = 0x10103
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// CHECK-NEXT: 10006: adr.w r3, #251
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// CHECK-NEXT: 1000a: nop
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/// AlignDown(0x1000c+4, 4) + 0xfff = 0x1100f
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// CHECK-NEXT: 1000c: adr.w r0, #4095
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/// AlignDown(0x10010+4, 4) + 0xffc = 0x11010
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// CHECK-NEXT: 10010: adr.w r1, #4092
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// CHECK-NEXT: 10014: nop
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/// AlignDown(0x10016+4, 4) + 0xff9 = 0x11011
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// CHECK-NEXT: 10016: adr.w r2, #4089
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/// AlignDown(0x1001a+4, 4) + 0xff6 = 0x11012
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// CHECK-NEXT: 1001a: adr.w r3, #4086
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/// AlignDown(0x1001e+4, 4) + 0xff7 = 0x11017 = dat5 + 8
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// CHECK-NEXT: 1001e: adr.w r4, #4087
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// CHECK: 00010100 <target3>:
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// CHECK-NEXT: 10100: bx lr
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// CHECK: 00010102 <target4>:
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// CHECK-NEXT: 10102: bx lr
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// SYMS: Name: dat5
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// SYMS-NEXT: Value: 0x1100F
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// SYMS: Name: dat6
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// SYMS-NEXT: Value: 0x11010
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// SYMS: Name: dat7
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// SYMS-NEXT: Value: 0x11011
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// SYMS: Name: dat8
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// SYMS-NEXT: Value: 0x11012
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