forked from OSchip/llvm-project
76 lines
1.8 KiB
TableGen
76 lines
1.8 KiB
TableGen
//===-- VEInstrFormats.td - VE Instruction Formats ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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class InstVE<dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction {
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field bits<64> Inst;
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let Namespace = "VE";
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let Size = 8;
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bits<8> op;
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let Inst{0-7} = op;
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let DecoderNamespace = "VE";
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field bits<64> SoftFail = 0;
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}
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class RM<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: InstVE<outs, ins, asmstr, pattern> {
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bits<1> cx = 0;
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bits<7> sx;
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bits<1> cy = 0;
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bits<7> sy;
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bits<1> cz = 0;
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bits<7> sz;
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bits<32> imm32 = 0;
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let op = opVal;
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let Inst{15} = cx;
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let Inst{14-8} = sx;
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let Inst{23} = cy;
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let Inst{22-16} = sy;
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let Inst{31} = cz;
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let Inst{30-24} = sz;
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let Inst{63-32} = imm32;
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}
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class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: RM<opVal, outs, ins, asmstr, pattern> {
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bits<1> cw = 0;
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bits<1> cw2 = 0;
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bits<4> cfw = 0;
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let imm32{0-23} = 0;
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let imm32{24} = cw;
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let imm32{25} = cw2;
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let imm32{26-27} = 0;
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let imm32{28-31} = cfw;
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}
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class CF<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: RM<opVal, outs, ins, asmstr, pattern> {
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bits<1> cx2;
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bits<2> bpf;
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bits<4> cf;
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let cx = 0;
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let sx{6} = cx2;
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let sx{5-4} = bpf;
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let sx{3-0} = cf;
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}
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// Pseudo instructions.
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]>
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: InstVE<outs, ins, asmstr, pattern> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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