forked from OSchip/llvm-project
185 lines
6.0 KiB
C++
185 lines
6.0 KiB
C++
//===-- AVRAsmPrinter.cpp - AVR LLVM assembly writer ----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to GAS-format AVR assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "AVR.h"
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#include "AVRMCInstLower.h"
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#include "AVRSubtarget.h"
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#include "MCTargetDesc/AVRInstPrinter.h"
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#include "TargetInfo/AVRTargetInfo.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "avr-asm-printer"
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namespace llvm {
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/// An AVR assembly code printer.
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class AVRAsmPrinter : public AsmPrinter {
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public:
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AVRAsmPrinter(TargetMachine &TM,
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std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) { }
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StringRef getPassName() const override { return "AVR Assembly Printer"; }
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void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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const char *ExtraCode, raw_ostream &O) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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const char *ExtraCode, raw_ostream &O) override;
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void emitInstruction(const MachineInstr *MI) override;
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private:
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const MCRegisterInfo &MRI;
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};
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void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI);
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break;
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case MachineOperand::MO_Immediate:
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O << MO.getImm();
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break;
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case MachineOperand::MO_GlobalAddress:
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O << getSymbol(MO.getGlobal());
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break;
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case MachineOperand::MO_ExternalSymbol:
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O << *GetExternalSymbolSymbol(MO.getSymbolName());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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O << *MO.getMBB()->getSymbol();
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break;
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default:
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llvm_unreachable("Not implemented yet!");
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}
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}
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bool AVRAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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const char *ExtraCode, raw_ostream &O) {
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// Default asm printer can only deal with some extra codes,
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// so try it first.
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bool Error = AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
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if (Error && ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0)
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return true; // Unknown modifier.
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if (ExtraCode[0] >= 'A' && ExtraCode[0] <= 'Z') {
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const MachineOperand &RegOp = MI->getOperand(OpNum);
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assert(RegOp.isReg() && "Operand must be a register when you're"
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"using 'A'..'Z' operand extracodes.");
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Register Reg = RegOp.getReg();
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unsigned ByteNumber = ExtraCode[0] - 'A';
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unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
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unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
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(void)NumOpRegs;
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const AVRSubtarget &STI = MF->getSubtarget<AVRSubtarget>();
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const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
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unsigned BytesPerReg = TRI.getRegSizeInBits(*RC) / 8;
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assert(BytesPerReg <= 2 && "Only 8 and 16 bit regs are supported.");
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unsigned RegIdx = ByteNumber / BytesPerReg;
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assert(RegIdx < NumOpRegs && "Multibyte index out of range.");
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Reg = MI->getOperand(OpNum + RegIdx).getReg();
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if (BytesPerReg == 2) {
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Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
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: AVR::sub_lo);
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}
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O << AVRInstPrinter::getPrettyRegisterName(Reg, MRI);
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return false;
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}
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}
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if (Error)
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printOperand(MI, OpNum, O);
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return false;
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}
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bool AVRAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum, const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0]) {
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llvm_unreachable("This branch is not implemented yet");
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}
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const MachineOperand &MO = MI->getOperand(OpNum);
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(void)MO;
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assert(MO.isReg() && "Unexpected inline asm memory operand");
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// TODO: We should be able to look up the alternative name for
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// the register if it's given.
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// TableGen doesn't expose a way of getting retrieving names
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// for registers.
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if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
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O << "Z";
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} else {
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assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
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"Wrong register class for memory operand.");
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O << "Y";
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}
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// If NumOpRegs == 2, then we assume it is product of a FrameIndex expansion
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// and the second operand is an Imm.
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unsigned OpFlags = MI->getOperand(OpNum - 1).getImm();
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unsigned NumOpRegs = InlineAsm::getNumOperandRegisters(OpFlags);
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if (NumOpRegs == 2) {
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O << '+' << MI->getOperand(OpNum + 1).getImm();
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}
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return false;
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}
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void AVRAsmPrinter::emitInstruction(const MachineInstr *MI) {
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AVRMCInstLower MCInstLowering(OutContext, *this);
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MCInst I;
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MCInstLowering.lowerInstruction(*MI, I);
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EmitToStreamer(*OutStreamer, I);
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}
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} // end of namespace llvm
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAVRAsmPrinter() {
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llvm::RegisterAsmPrinter<llvm::AVRAsmPrinter> X(llvm::getTheAVRTarget());
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}
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