forked from OSchip/llvm-project
1385b27e92
Add specific scalar costs for CTLZ instructions, we can't discriminate between CTLZ and CTLZ_ZERO_UNDEF so we have to assume the worst. Given how BSR is often a microcoded nightmare on some older targets we might still be underestimating it. For targets supporting LZCNT (Intel Haswell+ or AMD Fam10+), we provide overrides that assume 1cy costs. llvm-svn: 374786 |
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AArch64 | ||
AMDGPU | ||
ARM | ||
NVPTX | ||
PowerPC | ||
SystemZ | ||
X86 | ||
XCore | ||
int_sideeffect.ll |