forked from OSchip/llvm-project
237 lines
12 KiB
TableGen
237 lines
12 KiB
TableGen
//===- ARMScheduleV7.td - ARM v7 Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the itinerary class data for the ARM v7 processors.
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//
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//===----------------------------------------------------------------------===//
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//
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// Scheduling information derived from "Cortex-A8 Technical Reference Manual".
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//
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// Dual issue pipeline so every itinerary starts with FU_Pipe0 | FU_Pipe1
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//
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def CortexA8Itineraries : ProcessorItineraries<[
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// Two fully-pipelined integer ALU pipelines
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//
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// No operand cycles
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InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
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//
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// Binary Instructions that produce a result
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InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
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InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 2]>,
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InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1]>,
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InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2, 1, 1]>,
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//
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// Unary Instructions that produce a result
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InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
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InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
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InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
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//
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// Compare instructions
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InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
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InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 2]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
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//
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// Move instructions, unconditional
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InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1]>,
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InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
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InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1]>,
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InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [1, 1, 1]>,
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//
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// Move instructions, conditional
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InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2]>,
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InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
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InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1]>,
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InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [2, 1, 1]>,
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// Integer multiply pipeline
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// Result written in E5, but that is relative to the last cycle of multicycle,
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// so we use 6 for those cases
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//
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InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>], [5, 1, 1]>,
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InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
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InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<2, [FU_Pipe0]>], [6, 1, 1]>,
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InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<2, [FU_Pipe0]>], [6, 1, 1, 4]>,
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InstrItinData<IIC_iMUL64 , [InstrStage<2, [FU_Pipe1], 0>,
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InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
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InstrItinData<IIC_iMAC64 , [InstrStage<2, [FU_Pipe1], 0>,
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InstrStage<3, [FU_Pipe0]>], [6, 6, 1, 1]>,
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// Integer load pipeline
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//
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// loads have an extra cycle of latency, but are fully pipelined
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// use FU_Issue to enforce the 1 load/store per cycle limit
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//
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// Immediate offset
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InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iLoadsi , [InstrStage<2, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0], 0>,
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InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [4, 1, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 2, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 2, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iLoadsiu , [InstrStage<2, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0], 0>,
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InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [4, 3, 1, 1]>,
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//
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// Load multiple
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InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Issue], 0>,
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InstrStage<2, [FU_Pipe0], 0>,
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InstrStage<2, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>]>,
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// Integer store pipeline
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//
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// use FU_Issue to enforce the 1 load/store per cycle limit
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//
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// Immediate offset
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InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1]>,
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//
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// Register offset
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InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>], [3, 1, 1]>,
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//
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// Scaled register offset, issues over 2 cycles
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InstrItinData<IIC_iStoresi , [InstrStage<2, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0], 0>,
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InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 1, 1]>,
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//
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// Immediate offset with update
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InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [2, 3, 1]>,
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//
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// Register offset with update
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InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [2, 3, 1, 1]>,
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//
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// Scaled register offset with update, issues over 2 cycles
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InstrItinData<IIC_iStoresiu, [InstrStage<2, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0], 0>,
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InstrStage<1, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>], [3, 3, 1, 1]>,
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//
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// Store multiple
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InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Issue], 0>,
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InstrStage<2, [FU_Pipe0], 0>,
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InstrStage<2, [FU_Pipe1], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>]>,
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// Branch
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//
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// no delay slots, so the latency of a branch is unimportant
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>,
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// NFP ALU is not pipelined so stall all issues
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InstrItinData<IIC_fpALU , [InstrStage<7, [FU_Pipe0], 0>,
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InstrStage<7, [FU_Pipe1], 0>]>,
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// VFP MPY is not pipelined so stall all issues
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InstrItinData<IIC_fpMPY , [InstrStage<7, [FU_Pipe0], 0>,
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InstrStage<7, [FU_Pipe1], 0>]>,
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// loads have an extra cycle of latency, but are fully pipelined
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_LdSt0]>]>,
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// use FU_Issue to enforce the 1 load/store per cycle limit
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Issue], 0>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>]>
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]>;
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// FIXME
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def CortexA9Itineraries : ProcessorItineraries<[
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InstrItinData<IIC_iALUx , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iALUsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iUNAsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMPsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVsi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iCMOVsr , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL16 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC16 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL32 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC32 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMUL64 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iMAC64 , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iLoadi , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadr , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadsi , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadiu , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadru , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadsiu, [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_iLoadm , [InstrStage<2, [FU_Pipe0]>,
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InstrStage<2, [FU_LdSt0]>]>,
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InstrItinData<IIC_iStorei , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStorer , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoresi , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoreiu , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoreru , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStoresiu, [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_iStorem , [InstrStage<2, [FU_Pipe0]>]>,
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InstrItinData<IIC_Br , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpALU , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpMPY , [InstrStage<1, [FU_Pipe0]>]>,
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InstrItinData<IIC_fpLoad , [InstrStage<1, [FU_Pipe0]>,
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InstrStage<1, [FU_LdSt0]>]>,
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InstrItinData<IIC_fpStore , [InstrStage<1, [FU_Pipe0]>]>
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]>;
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