forked from OSchip/llvm-project
fbb823891d
Summary: A *lot* of instructions have this special register. It seems this never really worked, but i finally noticed it only because it happened to break for `CMOV16rm` instruction. We serialized that register as "" (empty string), which is naturally 'ignored' during deserialization, so we re-create a `MCInst` with too few operands. And when we then happened to try to resolve variant sched class for this mis-serialized instruction, and the variant predicate tried to read an operand that was out of bounds since we got less operands, we crashed. Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=41448 | PR41448 ]]. Reviewers: craig.topper, courbet Reviewed By: courbet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60517 llvm-svn: 358153 |
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analysis-cluster-stabilization.test | ||
analysis-clustering-algorithms.test | ||
analysis-epsilons.test | ||
analysis-inconsistencies-uops-backwards.test | ||
analysis-inconsistencies-uops.test | ||
analysis-naive-cluster-stabilization.test | ||
analysis-naive-clusterization.test | ||
analysis-same-cluster-for-ops-in-different-sched-clusters.test | ||
analysis-uops-backwards.test | ||
analysis-uops-variant.test | ||
analysis-uops.test | ||
inverse_throughput-by-opcode-name.s | ||
latency-CMOV32rr.s | ||
latency-SBB8rr.s | ||
latency-by-opcode-name.s | ||
lit.local.cfg | ||
uops-ADD32mi8.s | ||
uops-ADD32mr.s | ||
uops-ADD32rm.s | ||
uops-BEXTR32rm.s | ||
uops-BSF16rm.s | ||
uops-BTR64mr.s | ||
uops-CMOV16rm-noreg.s | ||
uops-VFMADDSS4rm.s | ||
uops-XCHG64rr.s | ||
uops-by-opcode-name.s |