forked from OSchip/llvm-project
134 lines
5.2 KiB
C++
134 lines
5.2 KiB
C++
//===-- PTXInstrInfo.h - PTX Instruction Information ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PTX_INSTR_INFO_H
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#define PTX_INSTR_INFO_H
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#include "PTXRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "PTXGenInstrInfo.inc"
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namespace llvm {
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class PTXTargetMachine;
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class MachineSDNode;
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class SDValue;
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class SelectionDAG;
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class PTXInstrInfo : public PTXGenInstrInfo {
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private:
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const PTXRegisterInfo RI;
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PTXTargetMachine &TM;
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public:
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explicit PTXInstrInfo(PTXTargetMachine &_TM);
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virtual const PTXRegisterInfo &getRegisterInfo() const { return RI; }
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg, unsigned SrcReg,
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bool KillSrc) const;
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virtual bool copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DstReg, unsigned SrcReg,
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const TargetRegisterClass *DstRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const;
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
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// predicate support
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virtual bool isPredicated(const MachineInstr *MI) const;
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const;
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const;
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// PTX is fully-predicable
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virtual bool isPredicable(MachineInstr *MI) const { return true; }
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// branch support
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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// Memory operand folding for spills
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// TODO: Implement this eventually and get rid of storeRegToStackSlot and
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// loadRegFromStackSlot. Doing so will get rid of the "stack" registers
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// we currently use to spill, though I doubt the overall effect on ptxas
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// output will be large. I have yet to see a case where ptxas is unable
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// to see through the "stack" register usage and hence generates
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// efficient code anyway.
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// virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
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// MachineInstr* MI,
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// const SmallVectorImpl<unsigned> &Ops,
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// int FrameIndex) const;
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virtual void storeRegToStackSlot(MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MII,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass* RC,
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const TargetRegisterInfo* TRI) const;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MII,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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// static helper routines
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static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
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DebugLoc dl, EVT VT,
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SDValue Op1);
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static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
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DebugLoc dl, EVT VT,
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SDValue Op1, SDValue Op2);
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static void AddDefaultPredicate(MachineInstr *MI);
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static bool IsAnyKindOfBranch(const MachineInstr& inst);
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static bool IsAnySuccessorAlsoLayoutSuccessor(const MachineBasicBlock& MBB);
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static MachineBasicBlock *GetBranchTarget(const MachineInstr& inst);
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}; // class PTXInstrInfo
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} // namespace llvm
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#endif // PTX_INSTR_INFO_H
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