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Craig Topper 9471a7c898 [X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching. 
Canonicalize EQ/NE PCMPM to have build vector all zeros on the RHS so we don't have to pattern match it in both locations. This significantly reduces the number of isel patterns needed since we also had to multiply it out with loads being in either operand of the 'and' input node and in the 'and' masking node.

This removes over 24000 bytes from the isel table.

llvm-svn: 325526
 		2018-02-19 19:23:31 +00:00
..
GC
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GlobalISel [GISel]: Make GlobalISelEmitter rule prioritization compatible with selectionDAG 2018-02-16 22:37:15 +00:00
avx512-shuffles [X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel patterns instead. 2018-02-05 06:00:23 +00:00
3addr-16bit.ll [x86] add RUN line and auto-generate checks 2018-01-19 17:09:28 +00:00
3addr-or.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
3dnow-intrinsics.ll
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3dnow-schedule.ll [X86][MMX] Add missing scheduling class tag for EMMS/FEMMS 2018-02-12 15:52:59 +00:00
4char-promote.ll
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2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2006-03-01-InstrSchedBug.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll
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2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll
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2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
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2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-27-LDIntrinsics.ll
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2007-10-04-AvoidEFLAGSCopy.ll
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2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
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2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2007-10-16-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
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2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
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2008-04-17-CoalescerBug.ll
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2008-04-24-MemCpyBug.ll
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2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
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2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
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2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll [X86][SSE] Regenerate old sitofp v2i32 test 2018-02-10 14:45:58 +00:00
2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug.ll
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2008-09-11-CoalescerBug2.ll
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll
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2008-10-06-x87ld-nan-1.ll
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2008-10-06-x87ld-nan-2.ll
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2008-10-07-SSEISelBug.ll
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll
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2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-13-inlineasm-3.ll
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2008-11-29-ULT-Sign.ll
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2008-12-01-SpillerAssert.ll
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2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-02-IllegalResultType.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-22-dagcombine-5.ll
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2008-12-23-crazy-address.ll
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2008-12-23-dagcombine-6.ll
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-16-UIntToFP.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift.ll
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2009-01-31-BigShift2.ll
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2009-01-31-BigShift3.ll
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2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-12-SpillerBug.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll [X86] Auto-generate full checks. NFC 2018-02-04 23:48:51 +00:00
2009-03-03-BTHang.ll
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2009-03-03-BitcastLongDouble.ll
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2009-03-05-burr-list-crash.ll
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2009-03-07-FPConstSelect.ll
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2009-03-09-APIntCrash.ll
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2009-03-09-SpillerBug.ll
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2009-03-10-CoalescerBug.ll
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2009-03-12-CPAlignBug.ll
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2009-03-13-PHIElimBug.ll
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2009-03-16-PHIElimInLPad.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll
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2009-03-23-i80-fp80.ll
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2009-03-25-TestBug.ll
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2009-04-12-picrel.ll
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2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-04-scale.ll
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2009-05-08-InlineAsmIOffset.ll
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2009-05-11-tailmerge-crash.ll
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2009-05-19-SingleElementExtractElement.ll
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2009-05-23-available_externally.ll
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2009-05-23-dagcombine-shifts.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-03-Win64SpillXMM.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-05-VZextByteShort.ll
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2009-06-05-VariableIndexInsert.ll
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2009-06-05-sitofpCrash.ll
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2009-06-06-ConcatVectors.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll
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2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll
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2009-08-14-Win64MemoryIndirectArg.ll
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2009-08-19-LoadNarrowingMiscompile.ll
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-16-CoalescerBug.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-EmergencySpill.ll
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2009-10-19-atomic-cmp-eflags.ll [X86] Teach DAG unfoldMemoryOperand to reconvert CMPs to tests 2018-02-05 18:58:58 +00:00
2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-01-05-ZExt-Shl.ll
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2010-01-07-ISelBug.ll
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2010-01-08-Atomic64Bug.ll
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2010-01-11-ExtraPHIArg.ll
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2010-01-13-OptExtBug.ll
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2010-01-15-SelectionDAGCycle.ll
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2010-01-18-DbgValue.ll
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2010-01-19-OptExtBug.ll
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2010-02-01-DbgValueCrash.ll
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2010-02-01-TaillCallCrash.ll
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2010-02-03-DualUndef.ll
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2010-02-04-SchedulerBug.ll
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2010-02-11-NonTemporal.ll
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2010-02-12-CoalescerBug-Impdef.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
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2010-02-23-DAGCombineBug.ll
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2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-RematImplicitSubreg.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
2010-03-17-ISelBug.ll
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2010-04-06-SSEDomainFixCrash.ll
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2010-04-08-CoalescerBug.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2010-04-13-AnalyzeBranchCrash.ll
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2010-04-21-CoalescerBug.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll
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2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
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2010-05-26-DotDebugLoc.ll
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2010-05-26-FP_TO_INT-crash.ll
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2010-05-28-Crash.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
2010-06-01-DeadArg-DbgInfo.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2010-06-25-asm-RA-crash.ll
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2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-UnfoldBug.ll
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2010-07-02-asm-alignstack.ll
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2010-07-06-DbgCrash.ll
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2010-07-06-asm-RIP.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
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2010-07-29-SetccSimplify.ll
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2010-08-04-MaskedSignedCompare.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2010-08-04-MingWCrash.ll
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2010-08-04-StackVariable.ll
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2010-09-01-RemoveCopyByCommutingDef.ll
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2010-09-16-EmptyFilename.ll
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2010-09-16-asmcrash.ll
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2010-09-17-SideEffectsInChain.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2010-09-30-CMOV-JumpTable-PHI.ll
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2010-10-08-cmpxchg8b.ll
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2010-11-02-DbgParameter.ll
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2010-11-09-MOVLPS.ll
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2010-11-18-SelectOfExtload.ll
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2011-01-07-LegalizeTypesCrash.ll
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2011-01-10-DagCombineHang.ll
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2011-01-24-DbgValue-Before-Use.ll
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2011-02-04-FastRegallocNoFP.ll
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2011-02-12-shuffle.ll
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2011-02-21-VirtRegRewriter-KillSubReg.ll
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2011-02-23-UnfoldBug.ll
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2011-02-27-Fpextend.ll
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2011-03-02-DAGCombiner.ll
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2011-03-08-Sched-crash.ll
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2011-03-09-Physreg-Coalescing.ll
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2011-03-30-CreateFixedObjCrash.ll
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2011-04-13-SchedCmpJmp.ll
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2011-04-19-sclr-bb.ll
…
2011-05-09-loaduse.ll
…
2011-05-26-UnreachableBlockElim.ll
…
2011-05-27-CrossClassCoalescing.ll
…
2011-06-01-fildll.ll
…
2011-06-03-x87chain.ll
…
2011-06-06-fgetsign80bit.ll
…
2011-06-12-FastAllocSpill.ll
…
2011-06-14-PreschedRegalias.ll
…
2011-06-14-mmx-inlineasm.ll
…
2011-06-19-QuicksortCoalescerBug.ll
…
2011-07-13-BadFrameIndexDisplacement.ll
…
2011-08-23-PerformSubCombine128.ll
…
2011-08-23-Trampoline.ll
…
2011-08-29-BlockConstant.ll
…
2011-08-29-InitOrder.ll
…
2011-09-14-valcoalesce.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
2011-09-18-sse2cmp.ll
…
2011-09-21-setcc-bug.ll
…
2011-10-11-SpillDead.ll
…
2011-10-11-srl.ll
…
2011-10-12-MachineCSE.ll
…
2011-10-18-FastISel-VectorParams.ll
…
2011-10-19-LegelizeLoad.ll
…
2011-10-19-widen_vselect.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2011-10-21-widen-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2011-10-27-tstore.ll
…
2011-10-30-padd.ll
…
2011-11-07-LegalizeBuildVector.ll
…
2011-11-22-AVX2-Domains.ll
…
2011-11-30-or.ll
…
2011-12-06-AVXVectorExtractCombine.ll
…
2011-12-06-BitcastVectorGlobal.ll
…
2011-12-08-AVXISelBugs.ll
…
2011-12-8-bitcastintprom.ll [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied) 2018-01-22 12:05:17 +00:00
2011-12-15-vec_shift.ll
…
2011-12-26-extractelement-duplicate-load.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2011-12-28-vselecti8.ll
…
2011-20-21-zext-ui2fp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-01-10-UndefExceptionEdge.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2012-1-10-buildvector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-01-11-split-cv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-01-12-extract-sv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-01-16-mfence-nosse-flags.ll
…
2012-01-18-vbitcast.ll [X86] Remove duplicate CHECK-LABEL line the update script didn't delete when I converted the test. 2018-02-13 01:36:27 +00:00
2012-02-12-dagco.ll
…
2012-02-14-scalar.ll
…
2012-02-23-mmx-inlineasm.ll
…
2012-02-29-CoalescerBug.ll
…
2012-03-15-build_vector_wl.ll
…
2012-03-20-LargeConstantExpr.ll
…
2012-03-26-PostRALICMBug.ll
…
2012-04-09-TwoAddrPassBug.ll
…
2012-04-26-sdglue.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-05-17-TwoAddressBug.ll
…
2012-05-19-CoalescerCrash.ll
…
2012-07-10-extload64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-07-10-shufnorm.ll
…
2012-07-15-BuildVectorPromote.ll
…
2012-07-15-broadcastfold.ll
…
2012-07-15-tconst_shl.ll
…
2012-07-15-vshl.ll
…
2012-07-16-LeaUndef.ll
…
2012-07-16-fp2ui-i1.ll
…
2012-07-17-vtrunc.ll
…
2012-07-23-select_cc.ll
…
2012-08-07-CmpISelBug.ll
…
2012-08-16-setcc.ll [X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching 2018-02-01 17:08:39 +00:00
2012-08-17-legalizer-crash.ll
…
2012-08-28-UnsafeMathCrash.ll
…
2012-09-13-dagco-fneg.ll
…
2012-09-28-CGPBug.ll
…
2012-10-02-DAGCycle.ll
…
2012-10-03-DAGCycle.ll
…
2012-10-18-crash-dagco.ll
…
2012-11-28-merge-store-alias.ll
…
2012-12-1-merge-multiple.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
2012-12-12-DAGCombineCrash.ll
…
2012-12-14-v8fp80-crash.ll
…
2012-12-19-NoImplicitFloat.ll
…
2013-01-09-DAGCombineBug.ll
…
2013-03-13-VEX-DestReg.ll
…
2013-05-06-ConactVectorCrash.ll
…
2013-10-14-FastISel-incorrect-vreg.ll
…
2014-05-29-factorial.ll
…
2014-08-29-CompactUnwind.ll
…
9601.ll
…
20090313-signext.ll
…
AppendingLinkage.ll
…
Atomics-64.ll
…
DbgValueOtherTargets.test
…
DynamicCalleeSavedRegisters.ll
…
MachineBranchProb.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
MachineSink-CritEdge.ll
…
MachineSink-DbgValue.ll
…
MachineSink-PHIUse.ll
…
MachineSink-SubReg.ll
…
MachineSink-eflags.ll
…
MergeConsecutiveStores.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
O0-pipeline.ll [x86] Make the retpoline thunk insertion a machine function pass. 2018-01-31 20:56:37 +00:00
PR34565.ll [X86] Ignore DBG instructions in X86CmovConversion optimization to resolve PR34565 2017-10-15 11:00:56 +00:00
StackColoring-dbg.ll
…
StackColoring.ll
…
SwitchLowering.ll
…
SwizzleShuff.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
TruncAssertSext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
TruncAssertZext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
WidenArith.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
abi-isel.ll
…
absolute-bit-mask.ll [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem 2017-10-01 23:53:53 +00:00
absolute-bt.ll
…
absolute-cmp.ll
…
absolute-constant.ll
…
absolute-rotate.ll
…
add-ext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
add-i64.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
add-of-carry.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
add-sub-nsw-nuw.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
add.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
add32ri8.ll
…
add_shl_constant.ll
…
addcarry.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
addcarry2.ll [X86] Extend load-op-store fusion merge to ADC/SBB. 2018-01-19 15:37:57 +00:00
addr-label-difference.ll
…
addr-mode-matcher.ll
…
addr-of-ret-addr.ll
…
address-type-promotion-constantexpr.ll
…
adx-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
adx-schedule.ll [X86] Move ADX schedule tests out of schedule-x86_64.ll 2017-12-13 21:49:09 +00:00
aes-schedule.ll Reapply "[X86] Flag BroadWell scheduler model as complete" 2017-12-12 19:11:31 +00:00
aes_intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
alias-gep.ll
…
alias-static-alloca.ll
…
aliases.ll
…
aligned-comm.ll
…
aligned-variadic.ll
…
alignment-2.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
alignment.ll
…
all-ones-vector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
alldiv-divdi3.ll
…
alloca-align-rounding-32.ll
…
alloca-align-rounding.ll
…
allrem-moddi3.ll
…
and-encoding.ll [X86] Teach X86DAGToDAGISel::shrinkAndImmediate to preserve upper 32 zeroes of a 64 bit mask. 2018-02-05 16:54:07 +00:00
and-load-fold.ll
…
and-or-fold.ll
…
and-sink.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
and-su.ll Regenerate test results for and-su.ll . NFC 2018-01-27 16:00:10 +00:00
andimm8.ll
…
anyext.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
anyregcc-crash.ll
…
anyregcc.ll
…
apm.ll
…
arg-cast.ll
…
arg-copy-elide.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
asm-invalid-register-class-crasher.ll
…
asm-label.ll
…
asm-label2.ll
…
asm-mismatched-types.ll
…
asm-modifier-P.ll
…
asm-modifier.ll
…
asm-reg-type-mismatch.ll
…
asm-reject-reg-type-mismatch.ll
…
atom-call-reg-indirect-foldedreload32.ll
…
atom-call-reg-indirect-foldedreload64.ll
…
atom-call-reg-indirect.ll
…
atom-cmpb.ll
…
atom-fixup-lea1.ll
…
atom-fixup-lea2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
atom-fixup-lea3.ll
…
atom-fixup-lea4.ll
…
atom-lea-addw-bug.ll
…
atom-lea-sp.ll
…
atom-pad-short-functions.ll
…
atom-sched.ll
…
atom-shuf.ll
…
atomic-dagsched.ll
…
atomic-eflags-reuse.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
atomic-flags.ll
…
atomic-load-store-wide.ll
…
atomic-load-store.ll
…
atomic-minmax-i6432.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
atomic-non-integer.ll
…
atomic-ops-ancient-64.ll
…
atomic-or.ll
…
atomic-pointer.ll
…
atomic8.ll
…
atomic16.ll
…
atomic32.ll [X86] Regenerate atomic i32 tests 2018-02-07 13:28:23 +00:00
atomic64.ll
…
atomic128.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
atomic6432.ll
…
atomic_add.ll
…
atomic_idempotent.ll
…
atomic_mi.ll
…
atomic_op.ll
…
attribute-sections.ll
…
avg-mask.ll [X86] Legalize v32i1 without BWI via splitting to v16i1 rather than the default of promoting to v32i8. 2018-01-23 14:25:39 +00:00
avg.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
avoid-lea-scale2.ll
…
avoid-loop-align-2.ll
…
avoid-loop-align.ll
…
avoid_complex_am.ll
…
avx-arith.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-basic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-bitcast.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-brcond.ll Regenrate test results for avx-brcond.ll . NFC 2018-01-27 16:44:00 +00:00
avx-cast.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-cmp.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-cvt-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-cvt-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-cvt.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-fp2int.ll
…
avx-gfni-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-insertelt.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-intel-ocl.ll
…
avx-intrinsics-fast-isel.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-intrinsics-x86-upgrade.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-intrinsics-x86.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
avx-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-isa-check.ll
…
avx-load-store.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
avx-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-minmax.ll
…
avx-schedule.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
avx-select.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-shift.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-shuffle-x86_32.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-splat.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-trunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-unpack.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-varargs-x86_64.ll
…
avx-vbroadcast.ll [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value 2017-12-31 18:59:30 +00:00
avx-vbroadcastf128.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
avx-vextractf128.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-vinsertf128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-vpclmulqdq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx-vperm2x128.ll [X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector. 2018-02-09 05:54:34 +00:00
avx-vzeroupper.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx-win64-args.ll
…
avx-win64.ll
…
avx.ll
…
avx1-logical-load-folding.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-arith.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-conversions.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx2-fma-fneg-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-gather.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-intrinsics-fast-isel.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx2-intrinsics-x86-upgrade.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-masked-gather.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx2-nontemporal.ll [X86] Modify Nontemporal tests to avoid deadstore optimization. 2017-12-11 15:35:40 +00:00
avx2-phaddsub.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-pmovxrm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx2-schedule.ll [X86][SSE] Don't chain shuffles together in schedule tests 2018-02-03 21:20:19 +00:00
avx2-shift.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx2-vbroadcast.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
avx2-vbroadcasti128.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
avx2-vector-shifts.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx2-vperm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-adc-sbb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-any_extend_load.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-arith.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-bugfix-23634.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
avx512-bugfix-25270.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
avx512-bugfix-26264.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-build-vector.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-calling-conv.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
avx512-cmp-kor-sequence.ll [X86] Change signatures of avx512 packed fp compare intrinsics to return a vXi1 mask type to be closer to an fcmp. 2018-02-10 23:33:55 +00:00
avx512-cmp.ll Regenerate test. NFCI 2018-01-27 19:49:46 +00:00
avx512-cvt.ll [X86] Custom legalize (v2i32 (setcc (v2f32))) so that we don't end up with a (v4i1 (setcc (v4f32))) 2018-02-10 19:12:58 +00:00
avx512-ext.ll [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign extend and a shift. 2018-02-10 08:06:52 +00:00
avx512-extract-subvector-load-store.ll X86 Tests: Update more isel tests with FastVariableShuffle feature 2018-01-09 16:26:06 +00:00
avx512-extract-subvector.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-fma-commute.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-fma-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-fma.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-fsel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-gather-scatter-intrin.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-gfni-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-hadd-hsub.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-i1test.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-inc-dec.ll
…
avx512-insert-extract.ll [X86] Change some compare patterns to use loadi8/loadi16/loadi32/loadi64 helper fragments. 2018-02-12 02:48:42 +00:00
avx512-insert-extract_i1.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-intel-ocl.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
avx512-intrinsics-fast-isel.ll [X86] Remove kortest intrinsics and replace with native IR. 2018-02-08 20:16:06 +00:00
avx512-intrinsics-upgrade.ll [X86] Reverse the operand order of the autoupgrade of the kunpack builtins. 2018-02-12 22:38:34 +00:00
avx512-intrinsics.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
avx512-load-store.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-load-trunc-store-i1.ll [AVX512] Adding support for load truncate store of I1 2017-12-14 11:55:50 +00:00
avx512-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-mask-op.ll [X86] Teach combineInsertSubvector how to combine some k-register insert_subvectors and extract_subvector sequences to remove extra zeroing.wq 2018-02-10 01:00:41 +00:00
avx512-mask-spills.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-mask-zext-bugfix.ll [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and autoupgrade to (icmp slt X, 0) 2018-01-09 00:50:47 +00:00
avx512-masked-memop-64-32.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512-masked_memop-16-8.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-memfold.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-mov.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512-nontemporal.ll [X86] Modify Nontemporal tests to avoid deadstore optimization. 2017-12-11 15:35:40 +00:00
avx512-pmovxrm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-regcall-Mask.ll [X86] Legalize (i64 (bitcast (v64i1 X))) on 32-bit targets by extracting to v32i1 and bitcasting to i32. 2018-02-02 05:59:31 +00:00
avx512-regcall-NoMask.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
avx512-rotate.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-scalar.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
avx512-scalarIntrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-scalar_mask.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-schedule.ll [X86] Regnerate test to show scheduling comments. NFC 2018-02-15 02:14:20 +00:00
avx512-select.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-shift.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-shuffle-schedule.ll [X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel patterns instead. 2018-02-05 06:00:23 +00:00
avx512-skx-insert-subvec.ll [X86] Custom legalize vXi1 extract_subvector with KSHIFTR. 2017-12-30 06:45:43 +00:00
avx512-trunc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-unsafe-fp-math.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-vbroadcast.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-vbroadcasti128.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
avx512-vbroadcasti256.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-vec-cmp.ll [X86] Make masked pcmpeq commutable during isel so we can fold loads in other operand to the shorter encoding. 2018-02-18 02:37:33 +00:00
avx512-vec3-crash.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512-vpclmulqdq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-vpermv3-commute.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-vpternlog-commute.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
avx512-vselect-crash.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512-vselect.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512bw-arith.ll
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avx512bw-intrinsics-fast-isel.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
avx512bw-intrinsics-upgrade.ll [X86] Reverse the operand order of the autoupgrade of the kunpack builtins. 2018-02-12 22:38:34 +00:00
avx512bw-intrinsics.ll [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and autoupgrade to (icmp slt X, 0) 2018-01-09 00:50:47 +00:00
avx512bw-mask-op.ll [X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer. 2018-02-08 22:26:36 +00:00
avx512bw-mov.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512bw-vec-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512bw-vec-test-testn.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
avx512bwvl-arith.ll
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avx512bwvl-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512bwvl-intrinsics-upgrade.ll [X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer. 2018-02-08 22:26:36 +00:00
avx512bwvl-intrinsics.ll [X86] Remove llvm.x86.avx512.cvt*2mask.* intrinsics and autoupgrade to (icmp slt X, 0) 2018-01-09 00:50:47 +00:00
avx512bwvl-mov.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512bwvl-vec-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512bwvl-vec-test-testn.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
avx512cd-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512cd-intrinsics-upgrade.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512cd-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512cdvl-intrinsics-upgrade.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512cdvl-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512dq-intrinsics-upgrade.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512dq-intrinsics.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512dq-mask-op.ll [X86] Add DAG combine to constant fold a bitcast of a vXi1 constant build_vector into a scalar integer. 2018-02-08 22:26:36 +00:00
avx512dqvl-intrinsics-upgrade.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512dqvl-intrinsics.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512er-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512f-vec-test-testn.ll [X86] Reduce the number of isel pattern variations needed for VPTESTM/VPTESTNM matching. 2018-02-19 19:23:31 +00:00
avx512ifma-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512ifmavl-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vbmi-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vbmi2-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vbmi2vl-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vbmivl-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vl-arith.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512vl-intrinsics-fast-isel.ll [X86] Teach LowerBUILD_VECTOR to recognize pair-wise splats of 32-bit elements and use a 64-bit broadcast 2018-01-17 18:58:22 +00:00
avx512vl-intrinsics-upgrade.ll [X86] Change signatures of avx512 packed fp compare intrinsics to return a vXi1 mask type to be closer to an fcmp. 2018-02-10 23:33:55 +00:00
avx512vl-intrinsics.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
avx512vl-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vl-mov.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512vl-nontemporal.ll [X86] Modify Nontemporal tests to avoid deadstore optimization. 2017-12-11 15:35:40 +00:00
avx512vl-vbroadcast.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
avx512vl-vec-cmp.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
avx512vl-vec-masked-cmp.ll [X86] Use min/max for vector ult/ugt compares if avoids a sign flip. 2018-02-11 17:11:40 +00:00
avx512vl-vec-test-testn.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
avx512vl-vpclmulqdq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vl_vnni-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vlcd-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vnni-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vpopcntdq-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
avx512vpopcntdq-schedule.ll [X86] Add AVX512 VPOPCNTDQ schedule tests 2017-12-15 11:32:31 +00:00
bad-tls-fold.mir [x86] Fix nasty bug in the x86 backend that is essentially impossible to 2018-02-07 23:59:14 +00:00
barrier-sse.ll
…
barrier.ll
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base-pointer-and-cmpxchg.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
basic-promote-integers.ll
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bc-extract.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bigstructret.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bigstructret2.ll
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bit-piece-comment.ll
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bit-test-shift.ll
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bitcast-and-setcc-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-and-setcc-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-and-setcc-512.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-i256.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bitcast-int-to-vector-bool-sext.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-int-to-vector-bool-zext.ll [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign extend and a shift. 2018-02-10 08:06:52 +00:00
bitcast-int-to-vector-bool.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-int-to-vector.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-mmx.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
bitcast-setcc-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-setcc-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bitcast-setcc-512.ll [X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select between PACK*SDW/PACK*SWB 2018-02-14 18:23:58 +00:00
bitcast.ll
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bitcast2.ll
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bitcnt-false-dep.ll [X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to match skylake client. 2018-01-29 21:56:48 +00:00
bitreverse.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
block-placement.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
block-placement.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bmi-intrinsics-fast-isel-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bmi-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bmi-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bmi.ll [X86] Add combine to shrink 64-bit ands when one input is an any_extend and the other input guarantees upper 32 bits are 0. 2018-02-13 16:25:25 +00:00
bmi2-schedule.ll [X86] Add missing MULX32 schedule test 2017-12-13 22:43:55 +00:00
bmi2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bool-ext-inc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bool-simplify.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bool-vector.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bool-zext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
br-fold.ll
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branch_instruction_and_target_split_perf_nops.mir Fix tests after move to utohexstr. 2017-12-28 17:00:37 +00:00
branchfolding-catchpads.ll
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branchfolding-debugloc.ll
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branchfolding-landingpads.ll
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branchfolding-undef.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
brcond.ll Regenrate brcond.ll test results. NFC 2018-01-27 16:57:15 +00:00
break-anti-dependencies.ll
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break-false-dep.ll Separate ExecutionDepsFix into 4 parts: 2018-01-22 10:05:23 +00:00
broadcast-elm-cross-splat-vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
broadcastm-lowering.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bss_pagealigned.ll
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bswap-inline-asm.ll
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bswap-rotate.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bswap-vector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bswap-wide-int.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bswap.ll [X86] Autogenerate complete checks on a couple tests. NFC 2018-01-19 22:04:20 +00:00
bswap_tree.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bswap_tree2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bt.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
btq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
bug26810.ll Take into account the cost of local intervals when selecting split candidate. 2018-01-31 13:31:08 +00:00
build-vector-128.ll [X86][SSE] Don't vectorize splat buildvector of binops (PR30780) 2017-12-31 17:07:47 +00:00
build-vector-256.ll [X86][SSE] Don't vectorize splat buildvector of binops (PR30780) 2017-12-31 17:07:47 +00:00
build-vector-512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
buildvec-insertvec.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
bypass-slow-division-32.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bypass-slow-division-64.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
bypass-slow-division-tune.ll [CodeGenPrepare] Disable div bypass when working set size is huge. 2017-11-14 19:31:51 +00:00
byval-align.ll
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byval-callee-cleanup.ll
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byval.ll
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byval2.ll
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byval3.ll
…
byval4.ll
…
byval5.ll
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byval6.ll
…
byval7.ll
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cache-intrinsic.ll
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call-imm.ll
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call-push.ll
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cas.ll
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cast-vsel.ll [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686) 2017-12-29 14:41:50 +00:00
catch.ll
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catchpad-dynamic-alloca.ll
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catchpad-lifetime.ll
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catchpad-realign-savexmm.ll
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catchpad-regmask.ll
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catchpad-reuse.ll
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catchpad-weight.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
catchret-empty-fallthrough.ll
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catchret-fallthrough.ll
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catchret-regmask.ll
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cfi-xmm.ll [X86] Output cfi directives for saved XMM registers even if no GPRs are saved 2017-11-18 06:23:48 +00:00
cfi.ll
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cfstring.ll
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chain_order.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
change-compare-stride-1.ll
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change-compare-stride-trickiness-0.ll
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change-compare-stride-trickiness-1.ll
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change-compare-stride-trickiness-2.ll
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change-unsafe-fp-math.ll
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cleanuppad-inalloca.ll
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cleanuppad-large-codemodel.ll
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cleanuppad-realign.ll
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clear_upper_vector_element_bits.ll [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle 2018-02-16 14:57:25 +00:00
clflushopt-schedule.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
clflushopt.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
clobber-fi0.ll
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clwb-schedule.ll [X86] Add CLWB schedule test 2017-12-13 22:09:09 +00:00
clwb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
clz.ll [X86] Add test cases that exercise the BSR/BSF optimization combineCMov. 2018-02-06 21:47:04 +00:00
clzero-schedule.ll [X86] Add CLZERO schedule test 2017-12-11 15:53:12 +00:00
clzero.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cmov-double.ll
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cmov-fp.ll
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cmov-into-branch.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cmov-promotion.ll [X86] Allow CMOVs of constants to be sign extended from i32. 2018-02-16 07:16:15 +00:00
cmov-schedule.ll [X86] Add CMOV schedule tests 2017-12-10 20:46:57 +00:00
cmov.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cmovcmov.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
cmp-fast-isel.ll
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cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cmpxchg-clobber-flags.ll X86: Fix X86CallFrameOptimization to search for the COPY StackPointer 2017-10-24 07:38:29 +00:00
cmpxchg-i1.ll
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cmpxchg-i128-i1.ll
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cmpxchg8b_alloca_regalloc_handling.ll
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cmpxchg16b.ll
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coal-sections.ll
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coalesce-esp.ll
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coalesce-implicitdef.ll
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coalesce_commute_movsd.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
coalesce_commute_subreg.ll
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coalescer-commute1.ll
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coalescer-commute2.ll
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coalescer-commute3.ll
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coalescer-commute4.ll
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coalescer-commute5.ll
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coalescer-cross.ll
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coalescer-dce.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
coalescer-dce2.ll
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coalescer-identity.ll
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coalescer-remat.ll
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coalescer-subreg.ll
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coalescer-win64.ll
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code_placement.ll
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code_placement_align_all.ll
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code_placement_cold_loop_blocks.ll
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code_placement_eh.ll
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code_placement_ignore_succ_in_inner_loop.ll
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code_placement_loop_rotation.ll
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code_placement_loop_rotation2.ll
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code_placement_loop_rotation3.ll
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codegen-prepare-addrmode-sext.ll
…
codegen-prepare-cast.ll
…
codegen-prepare-crash.ll
…
codegen-prepare-extload.ll
…
codegen-prepare.ll
…
codemodel.ll
…
coff-comdat.ll
…
coff-comdat2.ll
…
coff-comdat3.ll
…
coff-feat00.ll
…
coff-no-dead-strip.ll [CodeGen] Ignore private symbols in llvm.used for COFF 2018-01-26 00:15:25 +00:00
coff-weak.ll
…
coldcc64.ll
…
combine-64bit-vec-binop.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-abs.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
combine-add.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-and.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
combine-avx-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-avx2-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-fabs.ll [X86][SSE] Add some basic FABS combine tests 2018-01-10 13:28:34 +00:00
combine-fcopysign.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
combine-lds.ll
…
combine-mul.ll [x86] remove duplicate undef tests; NFC 2018-02-09 17:46:38 +00:00
combine-multiplies.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-or.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
combine-pmuldq.ll [X86] Reimplement r321437 using custom lowering instead of as a DAG combine. 2017-12-27 19:09:40 +00:00
combine-rotates.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-sdiv.ll [x86] consolidate and add tests for undef binop folds; NFC 2018-02-08 23:21:44 +00:00
combine-sext-in-reg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-shl.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
combine-smax.ll [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types 2018-02-11 10:52:37 +00:00
combine-smin.ll [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types 2018-02-11 10:52:37 +00:00
combine-sra.ll [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle 2018-02-16 14:57:25 +00:00
combine-srem.ll [x86] consolidate and add tests for undef binop folds; NFC 2018-02-08 23:21:44 +00:00
combine-srl.ll [x86] remove duplicate undef tests; NFC 2018-02-09 17:46:38 +00:00
combine-sse41-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-sub.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
combine-testm-and.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
combine-udiv.ll [x86] consolidate and add tests for undef binop folds; NFC 2018-02-08 23:21:44 +00:00
combine-umax.ll [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types 2018-02-11 10:52:37 +00:00
combine-umin.ll [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types 2018-02-11 10:52:37 +00:00
combine-urem.ll [x86] consolidate and add tests for undef binop folds; NFC 2018-02-08 23:21:44 +00:00
commute-3dnow.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
commute-blend-avx2.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
commute-blend-sse41.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
commute-clmul.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
commute-fcmp.ll [X86] Add a DAG combine to combine (sext (setcc)) with VLX 2018-01-09 18:14:22 +00:00
commute-intrinsic.ll
…
commute-two-addr.ll
…
commute-vpclmulqdq-avx.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
commute-vpclmulqdq-avx512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
commute-xop.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
commuted-blend-mask.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
compact-unwind.ll
…
compare-add.ll
…
compare-global.ll
…
compare-inf.ll
…
compare_folding.ll
…
compiler_used.ll
…
complex-asm.ll
…
complex-fastmath.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
complex-fca.ll
…
compress_expand.ll [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV 2018-02-14 15:55:24 +00:00
computeKnownBits_urem.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
conditional-indecrement.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
conditional-tailcall-samedest.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
conditional-tailcall.ll
…
const-base-addr.ll
…
constant-combines.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
constant-hoisting-and.ll
…
constant-hoisting-bfi.ll
…
constant-hoisting-cmp.ll
…
constant-hoisting-optnone.ll
…
constant-hoisting-shift-immediate.ll
…
constant-pool-remat-0.ll
…
constant-pool-sharing.ll
…
constpool.ll
…
constructor.ll [COFF] Implement constructor priorities 2017-11-28 08:07:18 +00:00
convert-2-addr-3-addr-inc64.ll
…
copy-eflags.ll
…
copy-propagation.ll
…
copysign-constant-magnitude.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cpus.ll [X86] Add skeleton support for icelake CPU. 2017-11-19 01:12:00 +00:00
crash-O0.ll
…
crash-lre-eliminate-dead-def.ll
…
crash-nosse.ll
…
crash.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
critical-anti-dep-breaker.ll
…
critical-edge-split-2.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cse-add-with-overflow.ll
…
cstring.ll
…
ctpop-combine.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
cvt16.ll
…
cvtv2f32.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
cxx_tlscc64.ll
…
dag-fmf-cse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
dag-merge-fast-accesses.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
dag-optnone.ll
…
dag-rauw-cse.ll
…
dag-update-nodetomatch.ll
…
dagcombine-and-setcc.ll
…
dagcombine-buildvector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
dagcombine-cse.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
dagcombine-shifts.ll
…
dagcombine-unsafe-math.ll
…
darwin-bzero.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
darwin-no-dead-strip.ll
…
darwin-preemption.ll Represent runtime preemption in the IR. 2017-10-26 15:00:26 +00:00
darwin-quote.ll
…
darwin-tls.ll
…
dbg-baseptr.ll
…
dbg-changes-codegen-branch-folding.ll
…
dbg-changes-codegen.ll
…
dbg-combine.ll
…
dbg-line-0-no-discriminator.ll Re-submit r289925 (Update .debug_line section version to match DWARF version) 2017-12-04 21:27:46 +00:00
debug-nodebug-crash.ll
…
debugloc-argsize.ll
…
debugloc-no-line-0.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
deopt-bundles.ll
…
deopt-intrinsic-cconv.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
deopt-intrinsic.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
disable-tail-calls.ll
…
discontiguous-loops.ll
…
div-rem-simplify.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
div8.ll
…
divide-by-constant.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
divide-windows-itanium.ll
…
divrem.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
divrem8_ext.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
dllexport-x86_64.ll [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64 2018-01-17 23:55:23 +00:00
dllexport.ll [CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64 2018-01-17 23:55:23 +00:00
dllimport-x86_64.ll
…
dllimport.ll
…
dollar-name.ll
…
domain-reassignment.mir [X86] Don't emit KTEST instructions unless only the Z flag is being used 2018-02-08 07:45:55 +00:00
dont-trunc-store-double-to-float.ll
…
dropped_constructor.ll
…
dwarf-comp-dir.ll [DWARF] Regularize dumping strings from line tables. 2018-02-05 20:43:15 +00:00
dwarf-eh-prepare.ll
…
dwarf-headers.ll
…
dyn-stackalloc.ll
…
dyn_alloca_aligned.ll
…
dynamic-alloca-in-entry.ll
…
dynamic-alloca-lifetime.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
dynamic-allocas-VLAs.ll
…
dynamic-regmask.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
early-cfi-sections.ll
…
early-ifcvt-crash.ll
…
early-ifcvt.ll
…
eflags-copy-expansion.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
eh-frame-unreachable.ll
…
eh-label.ll Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00
eh-nolandingpads.ll
…
eh-null-personality.ll
…
eh-unknown.ll Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00
eh_frame.ll
…
element-wise-atomic-memory-intrinsics.ll
…
elf-associated.ll
…
elf-comdat.ll
…
elf-comdat2.ll
…
emit-big-cst.ll
…
empty-function.ll
…
empty-functions.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
empty-struct-return-type.ll
…
emutls-pic.ll
…
emutls-pie.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
emutls.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
emutls_generic.ll
…
epilogue.ll
…
equiv_with_fndef.ll
…
equiv_with_vardef.ll
…
evex-to-vex-compress.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
exception-label.ll
…
exedeps-movq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
exedepsfix-broadcast.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
expand-opaque-const.ll
…
expand-vr64-gr64-copy.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
extend.ll
…
extended-fma-contraction.ll
…
extern_weak.ll
…
extmul64.ll
…
extmul128.ll
…
extract-combine.ll
…
extract-concat.ll
…
extract-extract.ll
…
extract-insert.ll [DAGCombine] Handle out of range EXTRACT_VECTOR_ELT indices 2018-01-03 22:42:33 +00:00
extract-store.ll [X86] Remove 'NOREX' comment from the printing of _NOREX instructions. 2018-01-23 05:37:00 +00:00
extractelement-from-arg.ll
…
extractelement-index.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
extractelement-legalization-cycle.ll
…
extractelement-legalization-store-ordering.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
extractelement-load.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
extractelement-shuffle.ll
…
extractps.ll
…
f16c-intrinsics-fast-isel.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
f16c-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
f16c-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
fabs.ll
…
fadd-combines.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll
…
fast-cc-pass-in-regs.ll
…
fast-isel-abort-warm.ll
…
fast-isel-agg-constant.ll
…
fast-isel-args-fail.ll
…
fast-isel-args-fail2.ll
…
fast-isel-args.ll
…
fast-isel-atomic.ll
…
fast-isel-avoid-unnecessary-pic-base.ll
…
fast-isel-bail.ll
…
fast-isel-bc.ll
…
fast-isel-bitcasts-avx.ll
…
fast-isel-bitcasts-avx512.ll
…
fast-isel-bitcasts.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-bool.ll
…
fast-isel-call-cleanup.ll
…
fast-isel-call.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
fast-isel-cmp-branch.ll
…
fast-isel-cmp-branch2.ll
…
fast-isel-cmp-branch3.ll
…
fast-isel-cmp.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fast-isel-constant.ll
…
fast-isel-constpool.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-constrain-store-indexreg.ll
…
fast-isel-deadcode.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
fast-isel-divrem-x86-64.ll
…
fast-isel-divrem.ll
…
fast-isel-double-half-convertion.ll
…
fast-isel-emutls.ll
…
fast-isel-expect.ll
…
fast-isel-extract.ll
…
fast-isel-float-half-convertion.ll
…
fast-isel-fneg.ll
…
fast-isel-fold-mem.ll
…
fast-isel-fptrunc-fpext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-gc-intrinsics.ll
…
fast-isel-gep.ll
…
fast-isel-gv.ll
…
fast-isel-i1.ll
…
fast-isel-int-float-conversion-x86-64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-int-float-conversion.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-load-i1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-mem.ll
…
fast-isel-movsbl-indexreg.ll
…
fast-isel-nontemporal.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fast-isel-noplt-pic.ll FastISel: support no-PLT PIC calls on ELF x86_64 2017-12-15 00:32:09 +00:00
fast-isel-ret-ext.ll
…
fast-isel-select-cmov.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-select-cmov2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-select-cmp.ll
…
fast-isel-select-pseudo-cmov.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-select-sse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-select.ll
…
fast-isel-sext-zext.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fast-isel-sext.ll
…
fast-isel-shift.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fast-isel-sse12-fptoint.ll
…
fast-isel-stackcheck.ll
…
fast-isel-store.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-tailcall.ll
…
fast-isel-tls.ll
…
fast-isel-trunc-kill-subreg.ll
…
fast-isel-vecload.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fast-isel-x32.ll
…
fast-isel-x86-64.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
fast-isel-x86.ll
…
fast-isel.ll
…
fastcall-correct-mangling.ll
…
fastcc-2.ll
…
fastcc-byval.ll
…
fastcc-sret.ll
…
fastcc.ll
…
fastcc3struct.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-softfloat.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fastmath-float-half-conversion.ll
…
fcmove.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
fdiv-combine.ll [DAGCombine] foldBinOpIntoSelect can fail to constant fold in some cases. 2017-12-27 11:36:18 +00:00
fdiv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fentry-insertion.ll
…
field-extract-use-trunc.ll
…
fildll.ll
…
file-directive.ll
…
file-source-filename.ll
…
finite-libcalls.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
fixup-bw-copy.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fixup-bw-copy.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fixup-bw-inst.ll
…
fixup-bw-inst.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
fixup-lea.ll
…
fixup-sfb-32.ll [X86] Reduce Store Forward Block issues in HW - Recommit after fixing Bug 36346 2018-02-14 14:58:53 +00:00
fixup-sfb.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
float-asmprint.ll
…
float-conv-elim.ll
…
floor-soft-float.ll
…
fltused.ll [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
fltused_function_pointer.ll [NFC] fix trivial typos in comments and documents 2018-01-29 05:17:03 +00:00
fma-commute-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma-do-not-commute.ll
…
fma-fneg-combine.ll [X86] Improve coverage of fma negations. 2017-12-20 01:26:36 +00:00
fma-intrinsics-phi-213-to-231.ll
…
fma-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma-phi-213-to-231.ll
…
fma-scalar-memfold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma-schedule.ll [X86] Add FMA3 schedule tests 2017-12-14 11:30:01 +00:00
fma.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-commute-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-fneg-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-intrinsics-x86_64-folded-load.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-scalar-memfold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma4-schedule.ll [X86] Add FMA4 schedule tests 2017-12-14 11:40:54 +00:00
fma_patterns.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fma_patterns_wide.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fmaddsub-combine.ll [X86] Add test cases that show cases where buildvector of extract and inserts should be turned into fmsubadd. 2017-12-17 18:31:36 +00:00
fmaxnum.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
fmf-flags.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
fminnum.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
fmsubadd-combine.ll [X86] Implement the fusing of MUL+SUBADD to FMSUBADD 2017-12-20 18:05:15 +00:00
fmul-combines.ll
…
fmul-zero.ll
…
fnabs.ll
…
fold-add.ll
…
fold-and-shift.ll
…
fold-call-2.ll
…
fold-call-3.ll
…
fold-call-oper.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load-binops.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fold-load-unops.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fold-load-vec.ll
…
fold-load.ll
…
fold-mul-lohi.ll
…
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll
…
fold-push.ll
…
fold-rmw-ops.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fold-sext-trunc.ll
…
fold-tied-op.ll
…
fold-vector-bv-crash.ll
…
fold-vector-sext-crash.ll [X86] Turn selects with constant condition into vector shuffles during DAG combine 2018-02-17 00:30:30 +00:00
fold-vector-sext-crash2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fold-vector-sext-zext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fold-vector-shl-crash.ll
…
fold-vector-shuffle-crash.ll
…
fold-vector-trunc-sitofp.ll
…
fold-vex.ll
…
fold-xmm-zero.ll
…
fold-zext-trunc.ll
…
fops-windows-itanium.ll
…
force-align-stack-alloca.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
force-align-stack.ll
…
fp-double-rounding.ll
…
fp-elim-and-no-fp-elim.ll
…
fp-elim.ll
…
fp-fast.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-immediate-shorten.ll
…
fp-in-intregs.ll
…
fp-intrinsics.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
fp-load-trunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-logic-replace.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-select-cmp-and.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-stack-2results.ll
…
fp-stack-O0-crash.ll
…
fp-stack-O0.ll
…
fp-stack-compare-cmov.ll
…
fp-stack-compare.ll
…
fp-stack-direct-ret.ll
…
fp-stack-ret-conv.ll
…
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
…
fp-stack-set-st1.ll
…
fp-stack.ll
…
fp-trunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp-une-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp2sint.ll
…
fp128-calling-conv.ll
…
fp128-cast.ll Add support for emitting libcalls for x86_fp80 -> fp128 and vice-versa 2018-01-17 22:29:16 +00:00
fp128-compare.ll
…
fp128-extract.ll [X86] Regenerate fp128 test 2018-01-14 19:07:41 +00:00
fp128-g.ll
…
fp128-i128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
fp128-libcalls.ll
…
fp128-load.ll
…
fp128-select.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fp128-store.ll
…
fp_constant_op.ll
…
fp_load_cast_fold.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
fp_load_fold.ll
…
fpcmp-soft-fp.ll
…
fpstack-debuginstr-kill.ll
…
frame-base.ll
…
frame-lowering-debug-intrinsic-2.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
frame-lowering-debug-intrinsic.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
frame-order.ll
…
frameaddr.ll
…
frameregister.ll
…
frem-msvc32.ll
…
fsgsbase-schedule.ll [X86] Add fsgsbase schedule tests. 2017-12-11 13:25:02 +00:00
fsgsbase.ll [X86] Regenerate fsgsbase intrinsic tests. NFCI. 2017-12-11 12:22:15 +00:00
fsxor-alignment.ll
…
full-lsr.ll
…
funclet-layout.ll
…
function-alias.ll
…
function-subtarget-features-2.ll
…
function-subtarget-features.ll
…
ga-offset.ll
…
ga-offset2.ll
…
gather-addresses.ll [X86] Add combine to shrink 64-bit ands when one input is an any_extend and the other input guarantees upper 32 bits are 0. 2018-02-13 16:25:25 +00:00
gcc_except_table.ll
…
gcc_except_table_functions.ll
…
gep-expanded-vector.ll
…
getelementptr.ll
…
gfni-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ghc-cc.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
ghc-cc64.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
global-access-pie-copyrelocs.ll Handle undefined weak hidden symbols on all architectures. 2017-10-27 21:18:48 +00:00
global-access-pie.ll
…
global-fill.ll
…
global-sections-comdat.ll
…
global-sections-tls.ll
…
global-sections.ll
…
gnu-seh-nolpads.ll
…
gpr-to-mask.ll [X86] Allow zextload/extload i1->i8 to be folded into instructions during isel 2018-02-12 01:33:36 +00:00
greedy_regalloc_bad_eviction_sequence.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
gs-fold.ll
…
h-register-addressing-32.ll
…
h-register-addressing-64.ll
…
h-register-store.ll
…
h-registers-0.ll
…
h-registers-1.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
h-registers-2.ll
…
h-registers-3.ll
…
haddsub-2.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
haddsub-3.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
haddsub-shuf.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
haddsub-undef.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
haddsub.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
half.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
handle-move.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
hhvm-cc.ll
…
hidden-vis-2.ll
…
hidden-vis-3.ll Use a got to access a hidden weak undefined on MachO. 2018-01-17 19:19:55 +00:00
hidden-vis-4.ll
…
hidden-vis-pic.ll
…
hidden-vis.ll
…
hipe-cc.ll
…
hipe-cc64.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
hipe-prologue.ll
…
hoist-common.ll
…
hoist-invariant-load.ll [X86] Preserve memory refs when folding loads into divides. 2017-11-08 22:26:39 +00:00
hoist-spill-lpad.ll
…
hoist-spill.ll
…
horizontal-reduce-smax.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
horizontal-reduce-smin.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
horizontal-reduce-umax.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
horizontal-reduce-umin.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
horizontal-shuffle.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
huge-stack-offset.ll
…
huge-stack-offset2.ll
…
i1narrowfail.ll
…
i2k.ll
…
i16lshr8pat.ll
…
i64-mem-copy.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
i64-to-float.ll [SelectionDAG] ComputeNumSignBits - add support for SMIN+SMAX clamp patterns 2018-02-17 22:19:50 +00:00
i128-and-beyond.ll
…
i128-immediate.ll
…
i128-mul.ll
…
i128-ret.ll
…
i128-sdiv.ll
…
i256-add.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
i386-setjmp-pic.ll
…
i386-shrink-wrapping.ll [X86] Change some compare patterns to use loadi8/loadi16/loadi32/loadi64 helper fragments. 2018-02-12 02:48:42 +00:00
i386-tlscall-fastregalloc.ll
…
i486-fence-loop.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
i686-win-shrink-wrapping.ll
…
iabs.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
ident-metadata.ll
…
ifunc-asm.ll
…
illegal-bitfield-loadstore.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
illegal-insert.ll
…
illegal-vector-args-return.ll
…
immediate_merging.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
immediate_merging64.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
implicit-null-check-negative.ll Fix implicit null check with negative offset 2017-10-17 11:47:36 +00:00
implicit-null-check.ll Fix implicit null check with negative offset 2017-10-17 11:47:36 +00:00
implicit-null-checks.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
implicit-use-spill.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
imul-lea-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
imul-lea.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
imul.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
inalloca-ctor.ll
…
inalloca-invoke.ll
…
inalloca-regparm.ll
…
inalloca-stdcall.ll
…
inalloca.ll
…
inconsistent_landingpad.ll
…
indirect-branch-tracking.ll Instrument Control Flow For Indirect Branch Tracking 2018-01-09 08:51:18 +00:00
indirect-hidden.ll
…
init-priority.ll
…
inline-0bh.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
inline-asm-2addr.ll
…
inline-asm-A-constraint.ll Allow usage of X86-prefixes as separate instrs. 2018-01-17 10:12:06 +00:00
inline-asm-R-constraint.ll
…
inline-asm-avx-v-constraint-32bit.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-avx-v-constraint.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-avx512f-v-constraint.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-avx512vl-v-constraint-32bit.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-avx512vl-v-constraint.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-bad-constraint-n.ll
…
inline-asm-duplicated-constraint.ll
…
inline-asm-error.ll
…
inline-asm-flag-clobber.ll
…
inline-asm-fpstack.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
inline-asm-h.ll
…
inline-asm-modifier-V.ll [X86] Support 'V' register operand modifier 2018-02-08 20:06:05 +00:00
inline-asm-modifier-n.ll
…
inline-asm-modifier-q.ll
…
inline-asm-mrv.ll
…
inline-asm-out-regs.ll
…
inline-asm-pic.ll
…
inline-asm-ptr-cast.ll
…
inline-asm-q-regs.ll
…
inline-asm-sp-clobber-memcpy.ll
…
inline-asm-stack-realign.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-stack-realign2.ll
…
inline-asm-stack-realign3.ll
…
inline-asm-tied.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
inline-asm-x-scalar.ll
…
inline-asm.ll
…
inline-sse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
inlineasm-sched-bug.ll
…
inreg.ll
…
ins_split_regalloc.ll
…
ins_subreg_coalesce-1.ll
…
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insert-into-constant-vector.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
insert-positions.ll
…
insertelement-copytoregs.ll
…
insertelement-duplicates.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
insertelement-legalize.ll
…
insertelement-ones.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
insertelement-shuffle.ll [DAGCombiner] Add a DAG combine to turn a splat build_vector where the splat elemnt is a bitcast from a vector type into a concat_vector 2018-01-18 04:17:06 +00:00
insertelement-zero.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
insertps-O0-bug.ll
…
insertps-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
insertps-from-constantpool.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
insertps-unfold-load-bug.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
int-intrinsic.ll
…
interval-update-remat.ll
…
invalid-liveness.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
invalid-shift-immediate.ll
…
ipra-inline-asm.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
ipra-local-linkage.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
ipra-reg-alias.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
ipra-reg-usage.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
ipra-transform.ll
…
isel-optnone.ll
…
isel-sink.ll
…
isel-sink2.ll
…
isel-sink3.ll
…
isint.ll
…
isnan.ll
…
isnan2.ll
…
ispositive.ll
…
jump_sign.ll [X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching 2018-02-01 17:08:39 +00:00
known-bits-vector.ll [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT 2018-02-17 21:49:40 +00:00
known-bits.ll [x86] shrink 'and' immediate values by setting the high bits (PR35907) 2018-01-19 16:37:25 +00:00
known-signbits-vector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
label-annotation.ll
…
label-redefinition.ll
…
lakemont.ll
…
large-code-model-isel.ll
…
large-constants.ll
…
large-gep-chain.ll
…
large-gep-scale.ll
…
large-global.ll
…
late-address-taken.ll
…
ldzero.ll
…
lea-2.ll
…
lea-3.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lea-4.ll
…
lea-5.ll
…
lea-opt-cse1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lea-opt-cse2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lea-opt-cse3.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lea-opt-cse4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lea-opt-memop-check-1.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
lea-opt-memop-check-2.ll
…
lea-opt-with-debug.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lea-opt.ll
…
lea-recursion.ll
…
lea.ll
…
lea32-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lea64-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
leaFixup32.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
leaFixup64.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
leaf-fp-elim.ll
…
legalize-fmp-oeq-vector-select.ll
…
legalize-libcalls.ll
…
legalize-shift-64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-shl-vec.ll [x86] preserve test intent by removing undef 2018-02-10 15:28:08 +00:00
legalize-sub-zero-2.ll
…
legalize-sub-zero.ll
…
legalizedag_vec.ll
…
libcall-sret.ll [X86] Do not generate __multi3 for mul i128 on X86 2017-10-21 02:26:00 +00:00
licm-dominance.ll
…
licm-nested.ll
…
licm-regpressure.ll
…
licm-symbol.ll
…
limited-prec.ll
…
linux-preemption.ll Represent runtime preemption in the IR. 2017-10-26 15:00:26 +00:00
lit.local.cfg
…
live-out-reg-info.ll [X86] Only reorder srl/and on last DAG combiner run 2018-02-16 18:51:09 +00:00
live-range-nosubreg.ll
…
liveness-local-regalloc.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
llc-override-mcpu-mattr.ll
…
load-combine-dbg.ll Debug Info: Fix the SDLoc propagation for a DAGCombiner rule 2017-10-10 18:08:32 +00:00
load-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
load-slice.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
loc-remat.ll
…
local_stack_symbol_ordering.ll
…
localescape.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
log2_not_readnone.ll
…
logical-load-fold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
long-setcc.ll
…
longlong-deadload.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
loop-blocks.ll
…
loop-hoist.ll
…
loop-search.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
loop-strength-reduce-2.ll
…
loop-strength-reduce-3.ll
…
loop-strength-reduce-crash.ll
…
loop-strength-reduce.ll
…
loop-strength-reduce2.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
…
loop-strength-reduce8.ll
…
lower-bitcast.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lower-vec-shift-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lower-vec-shift.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lower-vec-shuffle-bug.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lrshrink.ll
…
lsr-delayed-fold.ll
…
lsr-i386.ll
…
lsr-interesting-step.ll
…
lsr-loop-exit-cond.ll
…
lsr-negative-stride.ll
…
lsr-nonaffine.ll
…
lsr-normalization.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
lsr-overflow.ll
…
lsr-quadratic-expand.ll
…
lsr-redundant-addressing.ll
…
lsr-reuse-trunc.ll
…
lsr-reuse.ll
…
lsr-sort.ll
…
lsr-static-addr.ll
…
lsr-wrap.ll
…
lwp-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lwp-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
lwp-schedule.ll [X86] Add LWP schedule tests 2017-12-11 16:47:21 +00:00
lzcnt-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lzcnt-tzcnt.ll [X86] Auto-generate checks. NFC 2018-02-06 18:18:49 +00:00
lzcnt-zext-cmp.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
lzcnt.ll
…
machine-combiner-int-vec.ll [MachineCombiner] Add check for optimal pattern order. 2018-01-31 13:54:30 +00:00
machine-combiner-int.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-combiner.ll [MachineCombiner] Add check for optimal pattern order. 2018-01-31 13:54:30 +00:00
machine-copy-prop.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-cp.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
machine-cse.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-outliner-debuginfo.ll
…
machine-outliner-disubprogram.ll Add optional DICompileUnit to DIBuilder + make outliner debug info use it 2018-01-19 21:21:49 +00:00
machine-outliner-tailcalls.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
machine-outliner.ll [MachineOutliner] AArch64: Avoid saving + restoring LR if possible 2017-09-27 20:47:39 +00:00
machine-region-info.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
machine-sink-and-implicit-null-checks.ll
…
machine-sink.ll
…
machine-trace-metrics-crash.ll
…
machinesink-merge-debuginfo.ll Improve the test for r320216. NFC. 2017-12-20 19:11:31 +00:00
machinesink-null-debuginfo.ll Improve the test for r320216. NFC. 2017-12-20 19:11:31 +00:00
macho-comdat.ll
…
madd.ll [X86] Add more madd reduction tests with wider vectors. 2018-01-31 00:30:32 +00:00
mask-negated-bool.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
masked-iv-safe.ll
…
masked-iv-unsafe.ll
…
masked_gather_scatter.ll [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT 2018-02-17 21:49:40 +00:00
masked_memop.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
maskmovdqu.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
materialize.ll
…
mature-mc-support.ll
…
mbp-false-cfg-break.ll
…
mcinst-avx-lowering.ll
…
mcinst-lowering.ll
…
mcu-abi.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
mem-intrin-base-reg.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
mem-promote-integers.ll
…
membarrier.ll
…
memcmp-mergeexpand.ll [MergeICmps] Re-commit rL324317 "Enable the MergeICmps Pass by default." 2018-02-07 09:58:55 +00:00
memcmp-minsize.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
memcmp-optsize.ll [x86, MemCmpExpansion] allow 2 pairs of loads per block (PR33325) 2018-01-06 16:16:04 +00:00
memcmp.ll [x86, MemCmpExpansion] allow 2 pairs of loads per block (PR33325) 2018-01-06 16:16:04 +00:00
memcpy-2.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memcpy-from-string.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memcpy-struct-by-value.ll
…
memcpy.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
mempcpy-32.ll
…
mempcpy.ll
…
memset-2.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memset-3.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memset-nonzero.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
memset-sse-stack-realignment.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memset.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
memset64-on-x86-32.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
merge-consecutive-loads-128.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
merge-consecutive-loads-256.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
merge-consecutive-loads-512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
merge-consecutive-stores-i1.ll
…
merge-consecutive-stores.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
merge-sp-update-lea.ll
…
merge-store-constants.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
merge-store-partially-alias-loads.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
merge_store.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
merge_store_duplicated_loads.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mfence.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mingw-alloca.ll
…
misaligned-memset.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
misched-aa-colored.ll
…
misched-aa-mmos.ll
…
misched-balance.ll
…
misched-code-difference-with-debug.ll
…
misched-copy.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
misched-crash.ll
…
misched-fusion.ll
…
misched-ilp.ll
…
misched-matmul.ll
…
misched-matrix.ll
…
misched-new.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
mmx-arg-passing-x86-64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mmx-arg-passing.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mmx-arith.ll
…
mmx-bitcast-fold.ll
…
mmx-bitcast.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
mmx-coalescing.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mmx-copy-gprs.ll
…
mmx-cvt.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
mmx-fold-load.ll [X86][MMX] Improve MMX constant generation 2018-01-16 14:21:28 +00:00
mmx-fold-zero.ll [X86][MMX] Add support for MMX zero vector creation 2018-01-15 22:32:40 +00:00
mmx-intrinsics.ll
…
mmx-only.ll
…
mmx-schedule.ll [X86][MMX] Add missing scheduling class tag for EMMS/FEMMS 2018-02-12 15:52:59 +00:00
mod128.ll
…
movbe-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
movbe.ll
…
movfs.ll
…
movgs.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
movmsk.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
movntdq-no-avx.ll
…
movpc32-check.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
movtopush.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
movtopush.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
movtopush64.ll X86CallFrameOptimization: Recognize 'store 0/-1 using and/or' idioms 2017-10-24 12:13:05 +00:00
ms-inline-asm-avx512.ll
…
ms-inline-asm.ll
…
mul-constant-i16.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mul-constant-i32.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mul-constant-i64.ll [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions 2017-12-10 01:24:08 +00:00
mul-constant-result.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mul-i256.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
mul-i512.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
mul-i1024.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
mul-legalize.ll
…
mul-remat.ll
…
mul-shift-reassoc.ll
…
mul64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mul128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
mul128_sext_loop.ll
…
muloti.ll
…
mult-alt-generic-i686.ll
…
mult-alt-generic-x86_64.ll
…
mult-alt-x86.ll
…
multiple-loop-post-inc.ll
…
multiple-return-values-cross-block.ll
…
mulvi32.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
mulx32.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mulx64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
musttail-fastcall.ll
…
musttail-indirect.ll
…
musttail-thiscall.ll
…
musttail-varargs.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
musttail.ll
…
mwaitx-schedule.ll [X86] Add MWAITX/MONITORX schedule tests 2017-12-15 14:22:15 +00:00
mwaitx.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
nancvt.ll
…
narrow-shl-cst.ll
…
narrow-shl-load.ll
…
narrow_op-1.ll
…
neg-shl-add.ll
…
neg_cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
neg_fp.ll
…
negate-add-zero.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
negate-i1.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
negate-shift.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
negate.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
negative-offset.ll
…
negative-sin.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
negative-stride-fptosi-user.ll
…
negative-subscript.ll
…
negative_zero.ll
…
new-remat.ll
…
newline-and-quote.ll
…
no-and8ri8.ll
…
no-cmov.ll
…
no-plt.ll Improve testcase. 2018-01-29 19:37:27 +00:00
no-prolog-kill.ll
…
no-sse2-avg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
nobt.ll
…
nocx16.ll
…
non-lazy-bind.ll
…
non-unique-sections.ll
…
non-value-mem-operand.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
nonconst-static-ev.ll
…
nonconst-static-iv.ll
…
nontemporal-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
nontemporal-loads.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
nontemporal.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
noreturn-call.ll
…
norex-subreg.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
nosse-error1.ll
…
nosse-error2.ll
…
nosse-varargs.ll
…
nosse-vector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
not-and-simplify.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
note-sections.ll
…
null-streamer.ll
…
objc-gc-module-flags.ll
…
object-size.ll
…
oddshuffles.ll [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle 2018-02-16 14:57:25 +00:00
opaque-constant-asm.ll
…
opt-ext-uses.ll
…
opt-shuff-tstore.ll
…
opt_phis.mir Move tests to the correct place 2018-01-19 06:08:15 +00:00
optimize-max-0.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
optimize-max-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
optimize-max-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
optimize-max-3.ll
…
or-address.ll
…
or-branch.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
or-lea.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
osx-private-labels.ll
…
overflow-intrinsic-setcc-fold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
overflow.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
overlap-shift.ll
…
packed_struct.ll
…
packss.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
palignr.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
partial-fold32.ll
…
partial-fold64.ll
…
pass-three.ll
…
patchable-prologue.ll
…
patchpoint-invoke.ll Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00
patchpoint-verifiable.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
patchpoint-webkit_jscc.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
patchpoint.ll
…
pause.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
peep-setb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
peep-test-0.ll
…
peep-test-1.ll
…
peep-test-2.ll
…
peep-test-3.ll
…
peep-test-4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
peephole-cvt-sse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
peephole-fold-movsd.ll
…
peephole-multiple-folds.ll
…
peephole-na-phys-copy-folding.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
peephole-recurrence.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
peephole.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
personality.ll
…
personality_size.ll
…
phaddsub.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
phi-bit-propagation.ll
…
phi-immediate-factoring.ll
…
phielim-split.ll
…
phys-reg-local-regalloc.ll
…
phys_subreg_coalesce-2.ll
…
phys_subreg_coalesce-3.ll [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
phys_subreg_coalesce.ll
…
pic-load-remat.ll
…
pic.ll
…
pic_jumptable.ll
…
pie.ll
…
pku.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pmovext.ll
…
pmovsx-inreg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pmul.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
pmulld.ll
…
pointer-vector.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pop-stack-cleanup-msvc.ll [X86] Don't clobber reserved registers with stack adjustments 2017-11-07 08:50:21 +00:00
pop-stack-cleanup.ll
…
popcnt-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
popcnt.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
post-ra-sched-with-debug.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
post-ra-sched.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
postalloc-coalescing.ll
…
postra-licm.ll
…
powi.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
pr1462.ll
…
pr1489.ll
…
pr1505.ll
…
pr1505b.ll
…
pr2177.ll
…
pr2182.ll
…
pr2326.ll
…
pr2585.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr2656.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr2659.ll
…
pr2849.ll
…
pr2924.ll
…
pr2982.ll
…
pr3154.ll
…
pr3216.ll
…
pr3241.ll
…
pr3243.ll
…
pr3244.ll
…
pr3250.ll
…
pr3317.ll
…
pr3366.ll
…
pr3457.ll
…
pr3522.ll
…
pr5145.ll
…
pr7882.ll
…
pr9127.ll
…
pr9743.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
pr10068.ll
…
pr10475.ll
…
pr10499.ll
…
pr10523.ll
…
pr10524.ll
…
pr10525.ll
…
pr10526.ll
…
pr11202.ll
…
pr11334.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
pr11415.ll
…
pr11468.ll
…
pr11985.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
pr11998.ll
…
pr12360.ll [X86] Autogenerate complete checks on a couple tests. NFC 2018-01-19 22:04:20 +00:00
pr12889.ll
…
pr13209.ll
…
pr13220.ll
…
pr13458.ll
…
pr13577.ll [DAG] make binops with undef operands consistent with IR 2018-02-12 21:37:27 +00:00
pr13859.ll
…
pr13899.ll
…
pr14088.ll
…
pr14098.ll
…
pr14161.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr14204.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr14314.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr14333.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
pr14562.ll
…
pr15267.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr15296.ll
…
pr15309.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr15705.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr15981.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr16031.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr16360.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr16807.ll
…
pr17546.ll
…
pr17631.ll
…
pr17764.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr18014.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr18054.ll
…
pr18162.ll
…
pr18344.ll [X86][SSE] Don't colaesce v4i32 extracts 2018-01-26 17:11:34 +00:00
pr18846.ll
…
pr19049.ll
…
pr20011.ll [SelectionDAG] Fix codegen of vector stores with non byte-sized elements. 2018-01-20 16:05:10 +00:00
pr20012.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr20020.ll
…
pr20088.ll
…
pr21099.ll
…
pr21792.ll [X86][SSE] Don't colaesce v4i32 extracts 2018-01-26 17:11:34 +00:00
pr22019.ll
…
pr22103.ll
…
pr22338.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr22774.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr22970.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr23103.ll
…
pr23246.ll
…
pr23273.ll
…
pr23603.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr23664.ll
…
pr24139.ll
…
pr24374.ll
…
pr24602.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr25828.ll
…
pr26350.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr26625.ll
…
pr26652.ll
…
pr26757.ll
…
pr26835.ll
…
pr26870.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
pr27071.ll
…
pr27501.ll
…
pr27591.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr27681.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr28129.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr28173.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr28444.ll
…
pr28472.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr28489.ll
…
pr28504.ll
…
pr28515.ll
…
pr28560.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr28824.ll
…
pr29010.ll
…
pr29022.ll
…
pr29061.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr29112.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
pr29170.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr30284.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr30430.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr30511.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr30562.ll
…
pr30813.ll
…
pr31045.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr31088.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr31143.ll
…
pr31242.ll
…
pr31271.ll
…
pr31323.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr31773.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr31956.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
pr32108.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32241.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32256.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32278.ll
…
pr32282.ll Update test expectations after reverting PLT change 2018-02-06 00:56:06 +00:00
pr32284.ll [X86] Add combine to shrink 64-bit ands when one input is an any_extend and the other input guarantees upper 32 bits are 0. 2018-02-13 16:25:25 +00:00
pr32329.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr32340.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32345.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr32368.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32420.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32451.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32484.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr32515.ll
…
pr32588.ll
…
pr32610.ll
…
pr32659.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr32907.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr33290.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr33349.ll [X86] Make v2i1 and v4i1 legal types without VLX 2018-01-07 18:20:37 +00:00
pr33396.ll
…
pr33715.ll
…
pr33747.ll [X86] Add PR33747 test case 2018-02-11 13:12:50 +00:00
pr33772.ll
…
pr33828.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr33844.ll [x86] shrink 'and' immediate values by setting the high bits (PR35907) 2018-01-19 16:37:25 +00:00
pr33954.ll
…
pr33960.ll [DAG] make binops with undef operands consistent with IR 2018-02-12 21:37:27 +00:00
pr34080-2.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
pr34080.ll [X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently 2017-12-24 10:25:01 +00:00
pr34088.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
pr34137.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34139.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34149.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34177.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34271-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34271.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34381.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34397.ll
…
pr34421.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34592.ll [X86] Turn selects with constant condition into vector shuffles during DAG combine 2018-02-17 00:30:30 +00:00
pr34605.ll [X86] Use vmovdqu64/vmovdqa64 for unmasked integer vector stores for consistency with loads. 2018-01-18 07:44:09 +00:00
pr34629.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34634.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34653.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr34657.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr34855.ll [DAGCombiner] Support folding (mulhs/u X, 0)->0 for vectors. 2017-12-11 08:33:20 +00:00
pr35272.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
pr35316.ll [X86] Rename function main->foo in CodeGen/X86/pr35316.ll. NFC 2018-02-13 10:58:19 +00:00
pr35399.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pr35443.ll [X86] Rename function in recently added test case to not be 'main' returning 'void'. NFC 2017-12-07 17:02:49 +00:00
pr35636.ll [X86] Remove CompleteModel tags from CPU targets until we have better error checking (PR35636) 2017-12-12 16:12:53 +00:00
pr35761.ll [DAGCombine] Fix for PR35761 2018-01-08 13:21:24 +00:00
pr35763.ll [X86] Renamed CodeGen test 2018-01-08 10:56:44 +00:00
pr35765.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pr35918.ll [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied) 2018-01-22 12:05:17 +00:00
pr35972.ll [X86] When legalizing (v64i1 select i8, v64i1, v64i1) make sure not to introduce bitcasts to i64 in 32-bit mode 2018-01-17 18:46:01 +00:00
pr35982.ll [X86][MMX] Add PR35982 test cases 2018-01-17 22:19:31 +00:00
pr36199.ll [DAGCombiner] When folding (insert_subvector undef, (bitcast (extract_subvector N1, Idx)), Idx) -> (bitcast N1) make sure that N1 has the same total size as the original output 2018-02-01 20:48:50 +00:00
pre-coalesce-2.ll
…
pre-coalesce.ll
…
pre-coalesce.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
pre-ra-sched.ll
…
prefer-avx256-lzcnt.ll [X86] Teach X86 codegen to use vector width preference to avoid promoting to 512-bit types when VLX is enabled and the preference is for a smaller size. 2018-01-20 00:26:12 +00:00
prefer-avx256-mask-extend.ll [X86] Legalize zero extends from vXi1 to vXi16/vXi32/vXi64 using a sign extend and a shift. 2018-02-10 08:06:52 +00:00
prefer-avx256-mask-shuffle.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
prefer-avx256-popcnt.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
prefer-avx256-shift.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
prefer-avx256-trunc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
prefer-avx256-wide-mul.ll [X86] Teach X86 codegen to use vector width preference to avoid promoting to 512-bit types when VLX is enabled and the preference is for a smaller size. 2018-01-20 00:26:12 +00:00
prefetch.ll [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions. 2017-12-22 02:30:30 +00:00
prefixdata.ll
…
preserve_allcc64.ll
…
preserve_mostcc64.ll
…
private-2.ll
…
private.ll
…
prolog-push-seq.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
prologue-epilogue-remarks.mir [PEI] Fix failing test caused by r324283 2018-02-05 23:06:47 +00:00
prologuedata.ll
…
promote-assert-zext.ll
…
promote-i16.ll
…
promote-trunc.ll
…
promote-vec3.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
promote.ll [X86][SSE] Aggressively use PMADDWD for v4i32 multiplies with 17 or more leading zeros 2018-01-24 19:20:02 +00:00
ps4-noreturn.ll
…
pseudo_cmov_lower.ll
…
pseudo_cmov_lower1.ll
…
pseudo_cmov_lower2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pshufb-mask-comments.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
pshufd-combine-crash.ll
…
psubus.ll [X86][SSE] Use SplitBinaryOpsAndApply to recognise PSUBUS patterns before they're split on AVX1 2018-02-11 17:29:42 +00:00
ptest.ll [X86] Add avx512 command line to ptest.ll to demonstrate that 512-bit vectors are not handled by LowerVectorAllZeroTest. 2018-02-02 20:12:45 +00:00
ptr-rotate.ll
…
ptrtoint-constexpr.ll
…
push-cfi-debug.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
push-cfi-obj.ll Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00
push-cfi.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
ragreedy-bug.ll
…
ragreedy-hoist-spill.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
ragreedy-last-chance-recoloring.ll
…
rd-mod-wr-eflags.ll
…
rdpid-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
rdpid.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
rdpmc.ll [X86] Regenerate RDPMC intrinsic test 2018-01-19 12:05:58 +00:00
rdrand-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
rdrand-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rdrand.ll [LoopStrengthReduce, x86] don't add cost for a cmp that will be macro-fused (PR35681) 2018-02-05 23:43:05 +00:00
rdseed-schedule.ll [X86] Tag RDRAND/RDSEED instruction scheduler classes 2017-12-07 14:18:48 +00:00
rdseed-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rdseed.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rdtsc.ll [X86] Regenerate RDTSC codegen tests 2017-12-07 13:50:29 +00:00
read-fp-no-frame-pointer.ll
…
recip-fastmath.ll [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions 2017-12-10 01:24:08 +00:00
recip-fastmath2.ll [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int 2017-12-10 03:16:38 +00:00
recip-pic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
red-zone.ll
…
red-zone2.ll
…
reduce-trunc-shl.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
regalloc-advanced-split-cost.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
regalloc-reconcile-broken-hints.ll
…
regalloc-spill-at-ehpad.ll
…
regcall-no-plt.ll
…
reghinting.ll
…
regparm.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
regpressure.ll
…
rem.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rem_crash.ll
…
remat-constant.ll
…
remat-fold-load.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
remat-mov-0.ll
…
remat-phys-dead.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
remat-scalar-zero.ll
…
replace-load-and-with-bzhi.ll [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction. 2017-12-12 14:13:51 +00:00
replace_unsupported_masked_mem_intrin.ll
…
required-vector-width.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
ret-addr.ll
…
ret-i64-0.ll
…
ret-mmx.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
retpoline-external.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
retpoline-regparm.ll [X86] Use EDI for retpoline when no scratch regs are left 2018-02-13 20:47:49 +00:00
retpoline.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
return-ext.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
return_zeroext_i2.ll
…
returned-trunc-tail-calls.ll
…
reverse_branches.ll
…
rip-rel-address.ll
…
rip-rel-lea.ll
…
rodata-relocs.ll
…
rot16.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rot32.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rot64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rotate.ll [X86] Regenerate truncated rotation tests + add missing 32-bit checks 2017-12-17 18:20:42 +00:00
rotate2.ll
…
rotate4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rotate_vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
rounding-ops.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
rrlist-livereg-corrutpion.ll
…
rtm-schedule.ll [X86] Add RTM schedule tests 2017-12-15 14:37:28 +00:00
rtm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sad.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
sad_variations.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
saddo-redundant-add.ll
…
safestack.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
safestack_inline.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
safestack_ssp.ll
…
sandybridge-loads.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sar_fold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sar_fold64.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sbb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
scalar-extract.ll
…
scalar-fp-to-i64.ll Update test expectations after reverting PLT change 2018-02-06 00:56:06 +00:00
scalar-int-to-fp.ll [X86][AVX512] Add avx512dq fp2int/int2fp tests (PR31630) 2018-01-27 22:08:27 +00:00
scalar-min-max-fill-operand.ll
…
scalar_sse_minmax.ll
…
scalar_widen_div.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
scalarize-bitcast.ll
…
scatter-schedule.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
scavenger.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
scev-interchange.ll
…
schedule-x86-64-shld.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
schedule-x86_32.ll [X86] Don't swap argument on BOUND instruction in at&t syntax. 2018-02-14 21:54:58 +00:00
schedule-x86_64.ll [X86] Reverse the operand order of invlpga in at&t syntax to match gas. 2018-02-14 23:53:21 +00:00
scheduler-backtracking.ll
…
sdiv-exact.ll
…
sdiv-pow2.ll
…
segmented-stacks-dynamic.ll
…
segmented-stacks.ll [CodeGen] Emit necessary .note sections for -fsplit-stack 2017-09-27 19:34:00 +00:00
seh-catch-all-win32.ll
…
seh-catch-all.ll
…
seh-catchpad.ll
…
seh-except-finally.ll
…
seh-exception-code.ll
…
seh-filter-no-personality.ll
…
seh-finally.ll
…
seh-no-invokes.ll
…
seh-safe-div-win32.ll
…
seh-safe-div.ll
…
seh-stack-realign.ll
…
select-1-or-neg1.ll [x86] add select test to show there's no single right answer (PR28968); NFC 2018-02-12 22:19:24 +00:00
select-mmx.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
select-with-and-or.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
select.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
select_const.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
select_meta.ll
…
selectiondag-crash.ll
…
selectiondag-cse.ll
…
selectiondag-dominator.ll
…
selectiondag-order.ll
…
setcc-combine.ll [DAGCombine] Don't combine (and (setne X, 0), (setne X, -1)) --> (setuge (add X, 1), 2) for i1 2017-12-26 14:48:28 +00:00
setcc-logic.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
setcc-lowering.ll [X86] Allow KORTEST instruction to be used for testing if a mask is all ones 2018-02-08 07:54:16 +00:00
setcc-narrowing.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
setcc-wide-types.ll [x86] allow pairs of PCMPEQ for vector-sized integer equality comparisons (PR33325) 2018-01-02 16:38:29 +00:00
setcc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
setjmp-spills.ll
…
setoeq.ll
…
setuge.ll
…
sext-i1.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sext-load.ll
…
sext-ret-val.ll
…
sext-setcc-self.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sext-subreg.ll
…
sext-trunc.ll
…
sha-schedule.ll [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions 2017-12-10 01:24:08 +00:00
sha.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
shift-and.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shift-avx2-crash.ll
…
shift-bmi2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shift-coalesce.ll
…
shift-codegen.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shift-combine-crash.ll
…
shift-combine.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
shift-double-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shift-double.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
shift-folding.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shift-i128.ll
…
shift-i256.ll
…
shift-one.ll
…
shift-pair.ll [X86] Teach X86DAGToDAGISel::shrinkAndImmediate to preserve upper 32 zeroes of a 64 bit mask. 2018-02-05 16:54:07 +00:00
shift-parts.ll
…
shift-pcmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shl-anyext.ll
…
shl-crash-on-legalize.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shl-i64.ll
…
shl_elim.ll
…
shl_undef.ll
…
shrink-compare.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
shrink-fp-const1.ll
…
shrink-fp-const2.ll
…
shrink-wrap-chkstk.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
shrink_vmul.ll [X86][SSE] Aggressively use PMADDWD for v4i32 multiplies with 17 or more leading zeros 2018-01-24 19:20:02 +00:00
shrink_vmul_sse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shrink_wrap_dbg_value.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
shrinkwrap-hang.ll
…
shuffle-combine-crash-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
shuffle-combine-crash.ll
…
shuffle-of-insert.ll [DAGCombiner] eliminate shuffle of insert element 2017-12-07 15:17:58 +00:00
shuffle-of-splat-multiuses.ll X86 Tests: Update more isel tests with FastVariableShuffle feature 2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-128.ll X86 Tests: Update more isel tests with FastVariableShuffle feature 2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-256.ll X86 Tests: Update more isel tests with FastVariableShuffle feature 2018-01-09 16:26:06 +00:00
shuffle-strided-with-offset-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
shuffle-vs-trunc-128.ll [X86][AVX512] Add VBMI target shuffle-trunc tests 2018-01-30 16:01:41 +00:00
shuffle-vs-trunc-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
shuffle-vs-trunc-512.ll [X86][AVX512] Add VBMI target shuffle-trunc tests 2018-01-30 16:01:41 +00:00
sibcall-2.ll
…
sibcall-3.ll
…
sibcall-4.ll
…
sibcall-5.ll
…
sibcall-6.ll
…
sibcall-byval.ll
…
sibcall-win64.ll
…
sibcall.ll
…
simple-register-allocation-read-undef.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
simple-zext.ll
…
sincos-opt.ll
…
sincos.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sink-blockfreq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sink-cheap-instructions.ll
…
sink-gep-before-mem-inst.ll
…
sink-hoist.ll
…
sink-out-of-loop.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sjlj-baseptr.ll
…
sjlj-eh.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
sjlj.ll
…
slow-incdec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
slow-pmulld.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
slow-unaligned-mem.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
small-byval-memcpy.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
smul-with-overflow.ll
…
soft-fp-legal-in-HW-reg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
soft-fp.ll
…
soft-sitofp.ll
…
splat-const.ll
…
splat-for-size.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
split-eh-lpad-edges.ll
…
split-extend-vector-inreg.ll [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts 2018-02-15 12:14:15 +00:00
split-store.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
split-vector-bitcast.ll
…
split-vector-rem.ll
…
sqrt-fastmath-mir.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sqrt-fastmath-tune.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sqrt-fastmath.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
sqrt-partial.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sqrt.ll
…
sret-implicit.ll
…
sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-commute.ll
…
sse-domains.ll
…
sse-fcopysign.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-fsignum.ll [X86] Extend inputs with elements smaller than i32 to sint_to_fp/uint_to_fp before type legalization. 2018-02-10 17:58:58 +00:00
sse-intel-ocl.ll
…
sse-intrinsics-fast-isel-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-intrinsics-fast-isel.ll [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts 2018-02-15 12:14:15 +00:00
sse-intrinsics-x86-upgrade.ll [X86] Regenerate test checks in sse-intrinsics-x86-upgrade with update-llc 2018-01-01 09:00:13 +00:00
sse-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-load-ret.ll
…
sse-minmax.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-only.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-regcall.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
sse-scalar-fp-arith-unary.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse-scalar-fp-arith.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
sse-schedule.ll [X86][SSE] Don't chain shuffles together in schedule tests 2018-02-03 21:20:19 +00:00
sse-unaligned-mem-feature.ll
…
sse-varargs.ll
…
sse1.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
sse2-intrinsics-fast-isel-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse2-intrinsics-fast-isel.ll [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686) 2017-12-29 14:41:50 +00:00
sse2-intrinsics-x86-upgrade.ll [X86] Regenerate test checks in sse2-intrinsics-x86-upgrade with update-llc 2018-01-01 08:47:50 +00:00
sse2-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse2-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse2-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sse2-vector-shifts.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse3-avx-addsub-2.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
sse3-avx-addsub.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse3-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse3-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse3-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
sse3.ll [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying shuffle masks 2018-02-16 16:22:14 +00:00
sse4a-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse4a-schedule.ll Update BTVER2 sched numbers for some AVX instructions (xmm version). 2018-01-15 14:21:11 +00:00
sse4a-upgrade.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse4a.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse41-intrinsics-fast-isel.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
sse41-intrinsics-x86-upgrade.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
sse41-intrinsics-x86.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
sse41-pmovxrm.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse41-schedule.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
sse41.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
sse42-intrinsics-fast-isel-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse42-intrinsics-fast-isel.ll [X86] Add the 16 and 8-bit CRC32 instructions to the load folding tables. 2018-01-07 06:48:20 +00:00
sse42-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse42-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse42-schedule.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
sse_partial_update.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sse_reload_fold.ll
…
ssp-data-layout.ll
…
ssp-guard-spill.ll
…
ssse3-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ssse3-intrinsics-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ssse3-schedule.ll [X86][Haswell]: Updating the scheduling information for the Haswell subtarget. 2017-12-08 09:48:44 +00:00
stack-align-memcpy.ll
…
stack-align.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
stack-align2.ll
…
stack-folding-3dnow.ll
…
stack-folding-adx-x86_64.ll
…
stack-folding-bmi.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
stack-folding-bmi2.ll
…
stack-folding-fp-avx1.ll [X86][SSE] Force double domain for SHUFPD stack folding tests 2018-02-02 14:55:20 +00:00
stack-folding-fp-avx512.ll [X86] Change signatures of avx512 packed fp compare intrinsics to return a vXi1 mask type to be closer to an fcmp. 2018-02-10 23:33:55 +00:00
stack-folding-fp-avx512vl.ll [X86] Change signatures of avx512 packed fp compare intrinsics to return a vXi1 mask type to be closer to an fcmp. 2018-02-10 23:33:55 +00:00
stack-folding-fp-sse42.ll [X86][SSE] Force double domain for SHUFPD stack folding tests 2018-02-02 14:55:20 +00:00
stack-folding-int-avx1.ll
…
stack-folding-int-avx2.ll
…
stack-folding-int-avx512.ll [X86] Add DAG combine to turn (bitcast (and/or/xor (bitcast X), Y)) -> (and/or/xor X, (bitcast Y)) when casting between GPRs and mask operations. 2018-02-04 01:43:48 +00:00
stack-folding-int-avx512vl.ll [X86] Add VSHUFF32X4 and similar instructions to load folding tables. 2018-01-07 23:30:20 +00:00
stack-folding-int-sse42.ll [X86] Add the 16 and 8-bit CRC32 instructions to the load folding tables. 2018-01-07 06:48:20 +00:00
stack-folding-lwp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
stack-folding-mmx.ll
…
stack-folding-sha.ll
…
stack-folding-tbm.ll [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
stack-folding-x86_64.ll
…
stack-folding-xop.ll
…
stack-probe-red-zone.ll
…
stack-probe-size.ll
…
stack-probes.ll
…
stack-protector-dbginfo.ll
…
stack-protector-msvc.ll Re-commit r319490 "XOR the frame pointer with the stack cookie when protecting the stack" 2017-12-05 20:22:20 +00:00
stack-protector-remarks.ll
…
stack-protector-target.ll
…
stack-protector-vreg-to-vreg-copy.ll
…
stack-protector-weight.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
stack-protector.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
stack-size-section.ll [MC] Function stack size section. 2017-11-30 13:05:14 +00:00
stack-update-frame-opcode.ll
…
stack_guard_remat.ll
…
stackguard-internal.ll
…
stackmap-fast-isel.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
stackmap-frame-setup.ll
…
stackmap-large-constants.ll
…
stackmap-large-location-size.ll
…
stackmap-liveness.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
stackmap-nops.ll
…
stackmap-shadow-optimization.ll
…
stackmap.ll
…
stackpointer.ll
…
statepoint-allocas.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
statepoint-call-lowering.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
statepoint-far-call.ll
…
statepoint-forward.ll
…
statepoint-gctransition-call-lowering.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
statepoint-invoke.ll Emit smaller exception tables for non-SJLJ mode. 2018-02-09 17:13:37 +00:00
statepoint-live-in.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
statepoint-stack-usage.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
statepoint-stackmap-format.ll
…
statepoint-uniqueing.ll
…
statepoint-vector-bad-spill.ll
…
statepoint-vector.ll Regenerate test result for stateppint-vector.ll. NFC. 2018-01-27 17:16:26 +00:00
stdarg.ll
…
stdcall-notailcall.ll
…
stdcall.ll
…
store-empty-member.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
store-narrow.ll
…
store-zero-and-minus-one.ll
…
store_op_load_fold.ll
…
store_op_load_fold2.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
stores-merging.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
storetrunc-fp.ll
…
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
sub-with-overflow.ll
…
sub.ll
…
subcarry.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
subreg-to-reg-2.ll
…
subreg-to-reg-3.ll
…
subreg-to-reg-4.ll
…
subreg-to-reg-6.ll
…
subvector-broadcast.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
sunkaddr-ext.ll
…
swift-error.ll
…
swift-return.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
swiftcc.ll
…
swifterror.ll
…
swiftself.ll
…
switch-bt.ll [CodeGen] Peel off the dominant case in switch statement in lowering 2017-11-14 21:44:09 +00:00
switch-crit-edge-constant.ll
…
switch-default-only.ll
…
switch-density.ll
…
switch-edge-weight.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
switch-jump-table.ll [CodeGen] Unify the syntax of MBB successors in MIR and -debug output 2018-02-09 00:10:31 +00:00
switch-lower-peel-top-case.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
switch-or.ll
…
switch-order-weight.ll
…
switch-zextload.ll
…
switch.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
swizzle-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
swizzle-avx2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
system-intrinsics-64-xsave.ll
…
system-intrinsics-64-xsavec.ll
…
system-intrinsics-64-xsaveopt.ll
…
system-intrinsics-64-xsaves.ll
…
system-intrinsics-64.ll
…
system-intrinsics-xgetbv.ll [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
system-intrinsics-xsave.ll
…
system-intrinsics-xsavec.ll
…
system-intrinsics-xsaveopt.ll
…
system-intrinsics-xsaves.ll
…
system-intrinsics-xsetbv.ll
…
system-intrinsics.ll
…
tail-call-attrs.ll
…
tail-call-casts.ll
…
tail-call-conditional.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tail-call-got.ll
…
tail-call-legality.ll
…
tail-call-mutable-memarg.ll
…
tail-call-parameter-attrs-mismatch.ll
…
tail-call-win64.ll
…
tail-dup-addr.ll
…
tail-dup-catchret.ll
…
tail-dup-debugloc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tail-dup-merge-loop-headers.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
tail-dup-no-other-successor.ll
…
tail-dup-repeat.ll
…
tail-merge-after-mbp.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tail-merge-debugloc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tail-merge-identical.ll
…
tail-merge-unreachable.ll
…
tail-merge-wineh.ll
…
tail-opts.ll
…
tail-threshold.ll
…
tailcall-64.ll [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
tailcall-calleesave.ll
…
tailcall-cgp-dup.ll
…
tailcall-disable.ll
…
tailcall-fastisel.ll
…
tailcall-largecode.ll
…
tailcall-mem-intrinsics.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
tailcall-msvc-conventions.ll
…
tailcall-multiret.ll
…
tailcall-readnone.ll
…
tailcall-returndup-void.ll
…
tailcall-ri64.ll
…
tailcall-stackalign.ll
…
tailcall-structret.ll
…
tailcall.ll
…
tailcallbyval.ll
…
tailcallbyval64.ll
…
tailcallfp.ll
…
tailcallfp2.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallpic3.ll
…
tailcallstack64.ll
…
taildup-crash.ll
…
targetLoweringGeneric.ll
…
tbm-intrinsics-fast-isel-x86_64.ll [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
tbm-intrinsics-fast-isel.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
tbm-intrinsics-x86_64.ll [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
tbm-schedule.ll [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
tbm_patterns.ll [DAGCombiner] Add one use check to fold (not (and x, y)) -> (or (not x), (not y)) 2018-02-13 16:25:27 +00:00
test-nofold.ll
…
test-shrink-bug.ll [X86] Turn X86ISD::AND nodes that have no flag users back into ISD::AND just before isel to enable test instruction matching 2018-02-01 17:08:39 +00:00
test-shrink.ll [X86] Only reorder srl/and on last DAG combiner run 2018-02-16 18:51:09 +00:00
test-vs-bittest.ll [X86] Only reorder srl/and on last DAG combiner run 2018-02-16 18:51:09 +00:00
testb-je-fusion.ll [X86] Avoid using high register trick for test instruction 2018-01-31 16:48:54 +00:00
testl-commute.ll [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem 2017-10-01 23:53:53 +00:00
this-return-64.ll
…
tls-addr-non-leaf-function.ll
…
tls-android-negative.ll
…
tls-android.ll
…
tls-local-dynamic.ll
…
tls-models.ll
…
tls-pic.ll
…
tls-pie.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
tls-shrink-wrapping.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
tls-windows-itanium.ll
…
tls.ll
…
tlv-1.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
tlv-2.ll
…
tlv-3.ll
…
token_landingpad.ll
…
trap.ll
…
trunc-ext-ld-st.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
trunc-store.ll [SelectionDAG] Fix codegen of vector stores with non byte-sized elements. 2018-01-20 16:05:10 +00:00
trunc-subvector.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
trunc-to-bool.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
twoaddr-coalesce-2.ll
…
twoaddr-coalesce-3.ll
…
twoaddr-coalesce.ll
…
twoaddr-lea.ll
…
twoaddr-pass-sink.ll
…
twoaddr-sink-terminator.ll
…
uint64-to-float.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
uint_to_fp-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
uint_to_fp-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
uint_to_fp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
umul-with-carry.ll
…
umul-with-overflow.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unaligned-32-byte-memops.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
unaligned-load.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
unaligned-spill-folding.ll
…
undef-globals-bss.ll Place undefined globals in .bss instead of .data 2018-02-06 23:22:14 +00:00
undef-label.ll
…
undef-ops.ll [DAG] fix type of undef returned by getNode() 2018-02-13 14:55:07 +00:00
unknown-location.ll
…
unreachable-loop-sinking.ll
…
unreachable-mbb-undef-phi.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
unreachableblockelim.ll
…
unused_stackslots.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
unwind-init.ll
…
unwindraise.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
update-terminator-debugloc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
update-terminator.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
urem-i8-constant.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
urem-power-of-two.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
use-add-flags.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
utf8.ll
…
utf16-cfstrings.ll
…
v2f32.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
v4f32-immediate.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
v4i32load-crash.ll
…
v8i1-masks.ll [DAGCombiners] Don't turn ANDs to shuffles with zero so early. Give some other combines a chance to run. 2017-12-24 02:05:18 +00:00
vaargs.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx512-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vaes-intrinsics-avx512vl-x86.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
var-permute-128.ll Fix check-prefixes typo and line endings. 2018-02-01 22:32:41 +00:00
var-permute-256.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
var-permute-512.ll [SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left. 2017-12-22 17:18:13 +00:00
vararg-callee-cleanup.ll
…
vararg_no_start.ll
…
vararg_tailcall.ll
…
variable-sized-darwin-bzero.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
variadic-node-pic.ll
…
vastart-defs-eflags.ll [X86] Avoid using high register trick for test instruction 2018-01-31 16:48:54 +00:00
vbinop-simplify-bug.ll
…
vec-copysign-avx512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec-copysign.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec-loadsingles-alignment.ll
…
vec-trunc-store.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_add.ll
…
vec_align.ll
…
vec_align_i256.ll
…
vec_anyext.ll
…
vec_call.ll
…
vec_cast.ll
…
vec_cast2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_cmp_sint-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_cmp_uint-128.ll [X86] Use min/max for vector ult/ugt compares if avoids a sign flip. 2018-02-11 17:11:40 +00:00
vec_compare-sse4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_compare.ll
…
vec_ctbits.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_ext_inreg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_extract-avx.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
vec_extract-mmx.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_extract-sse4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_extract.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_fabs.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_floor.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
vec_fneg.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_fp_to_int.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vec_fpext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_fptrunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_i64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_ins_extract-1.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_ins_extract.ll
…
vec_insert-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_insert-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_insert-4.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_insert-5.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_insert-7.ll [SelectionDAG] SimplifyDemandedVectorElts - add support for VECTOR_INSERT_ELT 2018-02-17 21:49:40 +00:00
vec_insert-8.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_insert-9.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_insert-mmx.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vec_int_to_fp.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vec_loadsingles.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_logical.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_minmax_match.ll [X86] Use min/max for vector ult/ugt compares if avoids a sign flip. 2018-02-11 17:11:40 +00:00
vec_minmax_sint.ll [X86][SSE] Enable SMIN/SMAX/UMIN/UMAX custom lowering for all legal types 2018-02-11 10:52:37 +00:00
vec_minmax_uint.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vec_partial.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_reassociate.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_return.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_round.ll
…
vec_sdiv_to_shift.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-6.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-7.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-8.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-A.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-B.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-C.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-D.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-F.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_set-H.ll [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686) 2017-12-29 14:41:50 +00:00
vec_set.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_setcc-2.ll [X86] Use min/max for vector ult/ugt compares if avoids a sign flip. 2018-02-11 17:11:40 +00:00
vec_setcc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift4.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vec_shift5.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift6.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shift7.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_shuf-insert.ll
…
vec_split.ll
…
vec_ss_load_fold.ll [X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass. 2018-02-13 04:19:26 +00:00
vec_trunc_sext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_udiv_to_shift.ll
…
vec_uint_to_fp-fastmath.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_uint_to_fp.ll
…
vec_unsafe-fp-math.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vec_zero-2.ll
…
vec_zero.ll
…
vec_zero_cse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-bitreverse.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-blend.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-compare-all_of.ll [X86] Allow CMOVs of constants to be sign extended from i32. 2018-02-16 07:16:15 +00:00
vector-compare-any_of.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-compare-combines.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-compare-results.ll [X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select between PACK*SDW/PACK*SWB 2018-02-14 18:23:58 +00:00
vector-compare-simplify.ll [x86] add baseline vector compare tests for D42948; NFC 2018-02-14 16:15:15 +00:00
vector-extend-inreg.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-gep.ll
…
vector-half-conversions.ll Bring back r323297. 2018-02-19 16:02:38 +00:00
vector-idiv-sdiv-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-idiv-sdiv-256.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-idiv-sdiv-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-idiv-udiv-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-idiv-udiv-256.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-idiv-udiv-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-idiv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-interleave.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-intrinsics.ll
…
vector-lzcnt-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-lzcnt-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-lzcnt-512.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
vector-merge-store-fp-constants.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-mul.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-narrow-binop.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-pcmp.ll [X86][AVX2] Combine extract(broadcast(scalar_value)) --> scalar_value 2017-12-31 18:59:30 +00:00
vector-popcnt-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-popcnt-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-popcnt-512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-rem.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-rotate-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-rotate-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-rotate-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-sext.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-shift-ashr-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-shift-ashr-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-shift-ashr-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-shift-lshr-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-shift-lshr-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-shift-lshr-512.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-shift-shl-128.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-shift-shl-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-shift-shl-512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-128-v2.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
vector-shuffle-128-v4.ll [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying shuffle masks 2018-02-16 16:22:14 +00:00
vector-shuffle-128-v8.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
vector-shuffle-128-v16.ll [X86][SSE] Match PSHUFLW/PSHUFHW + PSHUFD vXi16 shuffle patterns (PR34686) 2017-12-29 14:41:50 +00:00
vector-shuffle-256-v4.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-shuffle-256-v8.ll [X86][SSE] Simplify demanded elements from BROADCAST shuffle source. 2018-01-27 19:48:13 +00:00
vector-shuffle-256-v16.ll [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. 2018-01-27 20:19:09 +00:00
vector-shuffle-256-v32.ll X86 Tests: Add shuffle that can be improved by widening elements. NFC 2018-02-04 19:31:14 +00:00
vector-shuffle-512-v8.ll [X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector. 2018-02-09 05:54:34 +00:00
vector-shuffle-512-v16.ll [X86] Remove X86ISD::SHUF128 from combineBitcastForMaskedOp. Use isel patterns instead. 2018-02-05 06:00:23 +00:00
vector-shuffle-512-v32.ll [X86] Use PSHUFB for v32i16 shuffles before falling back to VPERMW/VPERMI2W. 2017-12-21 08:22:51 +00:00
vector-shuffle-512-v64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-avx512.ll [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts 2018-02-15 12:14:15 +00:00
vector-shuffle-combining-avx.ll [X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector. 2018-02-09 05:54:34 +00:00
vector-shuffle-combining-avx2.ll [SelectionDAG] Enable SimplifyDemandedVectorElts support for simplifying shuffle masks 2018-02-16 16:22:14 +00:00
vector-shuffle-combining-avx512bw.ll [X86] Remove isel patterns for using unmasked vmovdqa32/vmovdqu32 for integer vector loads. 2018-01-18 07:44:06 +00:00
vector-shuffle-combining-avx512bwvl.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-combining-avx512vbmi.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-combining-sse4a.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-combining-sse41.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-combining-ssse3.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
vector-shuffle-combining-xop.ll [X86][SSE] Simplify demanded elements from BROADCAST shuffle source. 2018-01-27 19:48:13 +00:00
vector-shuffle-combining.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-shuffle-masked.ll [X86] Add isel patterns for selecting masked SUBV_BROADCAST with bitcasts. Remove combineBitcastForMaskedOp. 2018-02-05 08:37:37 +00:00
vector-shuffle-mmx.ll [X86][MMX] Improve MMX constant generation 2018-01-16 14:21:28 +00:00
vector-shuffle-sse1.ll [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts 2018-02-15 12:14:15 +00:00
vector-shuffle-sse4a.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-sse41.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-v1.ll [SelectionDAG] Add initial implementation of TargetLowering::SimplifyDemandedVectorElts 2018-02-15 12:14:15 +00:00
vector-shuffle-v48.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-shuffle-variable-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-shuffle-variable-256.ll [DAG, X86] Revert r324797, r324491, and r324359. 2018-02-17 02:26:25 +00:00
vector-sqrt.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-trunc-math.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-trunc-packus.ll [SelectionDAG] ComputeKnownBits - add support for SMIN+SMAX clamp patterns 2018-02-19 18:08:16 +00:00
vector-trunc-ssat.ll [X86][SSE] combineTruncateWithSat - use truncateVectorWithPACK down to 64-bit subvectors 2018-02-19 13:29:20 +00:00
vector-trunc-usat.ll [X86][SSE] Add saturated truncation tests for storing illegal v8i8 types 2018-02-15 17:48:34 +00:00
vector-trunc.ll [X86][SSE] Allow float domain crossing if we are merging 2 or more shuffles and the root started as a float domain shuffle 2018-02-16 14:57:25 +00:00
vector-truncate-combine.ll Revert r307036 because of PR34919. 2017-10-12 00:24:52 +00:00
vector-tzcnt-128.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-tzcnt-256.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vector-tzcnt-512.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-unsigned-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector-variable-idx.ll
…
vector-variable-idx2.ll
…
vector-zext.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vector-zmov.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vector.ll
…
vectorcall.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
verifier-phi-fail0.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
verifier-phi.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
version_directive.ll
…
vfcmp.ll
…
viabs.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
virtual-registers-cleared-in-machine-functions-liveins.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
visibility.ll
…
visibility2.ll
…
vmaskmov-offset.ll [SelectionDAG][X86] Fix incorrect offset generated for VMASKMOV 2018-02-14 15:55:24 +00:00
vmovq.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
volatile.ll
…
vortex-bug.ll
…
vpshufbitqbm-intrinsics.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vselect-2.ll [X86][SSE] Add custom execution domain fixing for BLENDPD/BLENDPS/PBLENDD/PBLENDW (PR34873) 2018-01-15 22:18:45 +00:00
vselect-avx.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vselect-constants.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vselect-minmax.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
vselect-packss.ll [X86][SSE] truncateVectorWithPACK - Use src type instead of dst to select between PACK*SDW/PACK*SWB 2018-02-14 18:23:58 +00:00
vselect-pcmp.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
vselect-zero.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vselect.ll [X86] Add a few new test cases for shrunkblend combine 2018-02-08 18:34:25 +00:00
vshift-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift-4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift-5.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift-6.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vshift_scalar.ll
…
vshift_split.ll
…
vshift_split2.ll
…
vsplit-and.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
vzero-excess.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
warn-stack.ll
…
weak-undef.ll Handle undefined weak hidden symbols on all architectures. 2017-10-27 21:18:48 +00:00
weak.ll
…
weak_def_can_be_hidden.ll
…
webkit-jscc.ll
…
wide-fma-contraction.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
wide-integer-cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
wide-integer-fold.ll
…
widen_arith-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_arith-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_arith-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_arith-4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_arith-5.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_arith-6.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_bitops-0.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
widen_bitops-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-4.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-5.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_cast-6.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_compare-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_conv-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_conv-2.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_conv-3.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
widen_conv-4.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
widen_conversions.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_extract-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_load-0.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_load-1.ll
…
widen_load-2.ll [X86][SSE] Add ISD::VECTOR_SHUFFLE to faux shuffle decoding (Reapplied) 2018-01-22 12:05:17 +00:00
widen_load-3.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widen_shuffle-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
widened-broadcast.ll [X86][SSE] Simplify demanded elements from BROADCAST shuffle source. 2018-01-27 19:48:13 +00:00
win-alloca-expander.ll
…
win-catchpad-csrs.ll
…
win-catchpad-nested-cxx.ll
…
win-catchpad-nested.ll
…
win-catchpad-varargs.ll
…
win-catchpad.ll
…
win-cleanuppad.ll
…
win-funclet-cfi.ll
…
win-mixed-ehpersonality.ll
…
win32-eh-available-externally.ll [WinEH] Don't emit state stores or EH thunks for available_externally functions 2017-12-28 18:41:31 +00:00
win32-eh-states.ll
…
win32-eh.ll
…
win32-pic-jumptable.ll [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00
win32-preemption.ll Represent runtime preemption in the IR. 2017-10-26 15:00:26 +00:00
win32-seh-catchpad-realign.ll
…
win32-seh-catchpad.ll
…
win32-seh-nested-finally.ll
…
win32-spill-xmm.ll
…
win32_sret.ll
…
win64-jumptable.ll
…
win64-nosse-csrs.ll
…
win64_alloca_dynalloca.ll
…
win64_call_epi.ll
…
win64_eh.ll
…
win64_eh_leaf.ll
…
win64_eh_leaf2.ll
…
win64_frame.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
win64_nonvol.ll
…
win64_params.ll
…
win64_sibcall.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
win64_vararg.ll
…
win_chkstk.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
win_coreclr_chkstk.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
win_cst_pool.ll
…
windows-itanium-alloca.ll
…
wineh-coreclr.ll
…
wineh-exceptionpointer.ll
…
wineh-no-ehpads.ll
…
x32-cet-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x32-function_pointer-1.ll
…
x32-function_pointer-2.ll
…
x32-function_pointer-3.ll
…
x32-indirectbr.ll
…
x32-landingpad.ll
…
x32-lea-1.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x32-movtopush64.ll
…
x32-va_start.ll
…
x64-cet-intrinsics.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-16.ll
…
x86-32-intrcc.ll
…
x86-32-vector-calling-conv.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-baseptr.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
x86-64-bittest-logic.ll [X86] Add the test cases that were supposed to go with r325287. 2018-02-16 00:39:05 +00:00
x86-64-call.ll
…
x86-64-dead-stack-adjust.ll
…
x86-64-disp.ll
…
x86-64-double-precision-shift-left.ll [X86] Regenerate double shift tests 2018-01-13 16:55:28 +00:00
x86-64-double-precision-shift-right.ll [X86] Regenerate double shift tests 2018-01-13 16:55:28 +00:00
x86-64-double-shifts-Oz-Os-O2.ll [X86] Regenerate double shift tests 2018-01-13 16:55:28 +00:00
x86-64-double-shifts-var.ll
…
x86-64-extend-shift.ll
…
x86-64-flags-intrinsics.ll
…
x86-64-gv-offset.ll
…
x86-64-intrcc-nosse.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-64-intrcc.ll
…
x86-64-jumps.ll
…
x86-64-mem.ll
…
x86-64-ms_abi-vararg.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
…
x86-64-pic-5.ll
…
x86-64-pic-6.ll
…
x86-64-pic-7.ll
…
x86-64-pic-8.ll
…
x86-64-pic-9.ll
…
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-pic-12.ll
…
x86-64-pic.ll
…
x86-64-plt-relative-reloc.ll
…
x86-64-psub.ll [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 2018-01-05 20:55:12 +00:00
x86-64-ptr-arg-simple.ll
…
x86-64-ret0.ll
…
x86-64-shortint.ll
…
x86-64-sret-return-2.ll
…
x86-64-sret-return.ll
…
x86-64-stack-and-frame-ptr.ll
…
x86-64-static-relo-movl.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
x86-64-tls-1.ll
…
x86-64-varargs.ll
…
x86-big-ret.ll
…
x86-cmov-converter.ll [CGP] Re-enable Select in complex addressing mode. 2018-01-26 06:26:56 +00:00
x86-flags-intrinsics.ll
…
x86-fold-pshufb.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-framelowering-trap.ll Revert "Correct dwarf unwind information in function epilogue for X86" 2017-11-08 21:31:14 +00:00
x86-inline-asm-validation.ll
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x86-interleaved-access.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
x86-interleaved-check.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-interrupt_cc.ll [X86] When doing callee save/restore for k-registers make sure we don't use KMOVQ on non-BWI targets 2018-02-07 21:41:50 +00:00
x86-interrupt_cld.ll
…
x86-interrupt_vzeroupper.ll
…
x86-mixed-alignment-dagcombine.ll
…
x86-no_caller_saved_registers-preserve.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-no_caller_saved_registers.ll
…
x86-plt-relative-reloc.ll
…
x86-repmov-copy-eflags.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
x86-sanitizer-shrink-wrapping.ll
…
x86-setcc-int-to-fp-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-shifts.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-shrink-wrap-unwind.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
x86-shrink-wrapping.ll Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-17 03:05:33 +00:00
x86-store-gv-addr.ll
…
x86-upgrade-avx-vbroadcast.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86-upgrade-avx2-vbroadcast.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
x86-win64-shrink-wrapping.ll
…
x86_64-mul-by-const.ll
…
x87-schedule.ll [X86][X87] Fix typo in znver1 FIST/FISTT schedule patterns 2017-12-10 19:19:22 +00:00
x87.ll
…
xaluo.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xchg-nofold.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xmm-r64.ll
…
xmulo.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-ifma.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-intrinsics-fast-isel.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-intrinsics-x86_64-upgrade.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-intrinsics-x86_64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-mask-comments.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-pcmov.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xop-schedule.ll [X86] Add XOP schedule tests 2017-12-15 14:02:35 +00:00
xor-combine-debugloc.ll Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
xor-icmp.ll [X86] Only reorder srl/and on last DAG combiner run 2018-02-16 18:51:09 +00:00
xor-select-i1-combine.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
xor.ll
…
xray-attribute-instrumentation.ll
…
xray-custom-log.ll
…
xray-empty-firstmbb.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
xray-empty-function.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
xray-log-args.ll
…
xray-loop-detection.ll
…
xray-multiplerets-in-blocks.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
xray-section-group.ll
…
xray-selective-instrumentation-miss.ll
…
xray-selective-instrumentation.ll
…
xray-tail-call-sled.ll
…
xtest.ll
…
zero-remat.ll
…
zext-demanded.ll [TargetLowering] try to create -1 constant operand for math ops via demanded bits 2018-02-11 14:38:23 +00:00
zext-extract_subreg.ll
…
zext-fold.ll [x86] shrink 'and' immediate values by setting the high bits (PR35907) 2018-01-19 16:37:25 +00:00
zext-inreg-0.ll
…
zext-inreg-1.ll
…
zext-sext.ll
…
zext-shl.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
zext-trunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
zlib-longest-match.ll
…