llvm-project/llvm/test/CodeGen
Cong Hou 94710840fb Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed.
Currently, AnalyzeBranch() fails non-equality comparison between floating points
on X86 (see https://llvm.org/bugs/show_bug.cgi?id=23875). This is because this
function can modify the branch by reversing the conditional jump and removing
unconditional jump if there is a proper fall-through. However, in the case of
non-equality comparison between floating points, this can turn the branch
"unanalyzable". Consider the following case:

jne.BB1
jp.BB1
jmp.BB2
.BB1:
...
.BB2:
...

AnalyzeBranch() will reverse "jp .BB1" to "jnp .BB2" and then "jmp .BB2" will be
removed:

jne.BB1
jnp.BB2
.BB1:
...
.BB2:
...

However, AnalyzeBranch() cannot analyze this branch anymore as there are two
conditional jumps with different targets. This may disable some optimizations
like block-placement: in this case the fall-through behavior is enforced even if
the fall-through block is very cold, which is suboptimal.

Actually this optimization is also done in block-placement pass, which means we
can remove this optimization from AnalyzeBranch(). However, currently
X86::COND_NE_OR_P and X86::COND_NP_OR_E are not reversible: there is no defined
negation conditions for them.

In order to reverse them, this patch defines two new CondCode X86::COND_E_AND_NP
and X86::COND_P_AND_NE. It also defines how to synthesize instructions for them.
Here only the second conditional jump is reversed. This is valid as we only need
them to do this "unconditional jump removal" optimization.


Differential Revision: http://reviews.llvm.org/D11393

llvm-svn: 264199
2016-03-23 21:45:37 +00:00
..
AArch64 [CXX_FAST_TLS] Disable tail call when calling conventions are mismatched. 2016-03-18 23:41:51 +00:00
AMDGPU AMDGPU: Add SIWholeQuadMode pass 2016-03-21 20:28:33 +00:00
ARM CodeGen: check return types match when emitting tail call to builtin. 2016-03-22 19:14:38 +00:00
BPF BPF: emit an error message for unsupported signed division operation 2016-03-18 22:02:47 +00:00
CPP
Generic Move test/CodeGen/Generic/pr26652.ll to test/CodeGen/X86/pr26652.ll and test it only on X86. 2016-02-25 00:12:18 +00:00
Hexagon Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Inputs DI: Reverse direction of subprogram -> function edge. 2015-11-05 22:03:56 +00:00
MIR [MIR] Add a test case for the diagnostic of a wrongly typed generic instruction 2016-03-15 18:31:29 +00:00
MSP430 `MSP430InstrInfo::loadRegFromStackSlot` forgets to set register def. 2016-02-24 15:15:02 +00:00
Mips [mips][microMIPS] Delay slot filler modifications 2016-03-23 10:29:38 +00:00
NVPTX [NVPTX] Adds a new address space inference pass. 2016-03-20 20:59:20 +00:00
PowerPC Codegen: [PPC] Word Rotates are Zero Extending. 2016-03-23 19:51:22 +00:00
SPARC Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
SystemZ [SystemZ] Avoid LER on z13 due to partial register dependencies 2016-03-14 13:50:03 +00:00
Thumb Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT. 2016-02-26 19:40:34 +00:00
Thumb2 ARM: Introduce conservative load/store optimization mode 2016-03-02 19:20:00 +00:00
WebAssembly [WebAssembly] Implement the rotate instructions. 2016-03-22 18:01:49 +00:00
WinEH [WinEH] Make setjmp work correctly with EH 2016-02-29 19:16:03 +00:00
X86 Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed. 2016-03-23 21:45:37 +00:00
XCore [MC] Use .p2align instead of .align 2016-01-26 00:03:25 +00:00