forked from OSchip/llvm-project
40 lines
1.1 KiB
LLVM
40 lines
1.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}br_i1_phi:
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; SI: ; %bb
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; SI: s_mov_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], 0
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; SI: ; %bb2
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; SI: s_mov_b64 [[TMP]], exec
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; SI: ; %bb3
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; SI: s_and_saveexec_b64 {{s\[[0-9]+:[0-9]+\]}}, [[TMP]]
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define amdgpu_kernel void @br_i1_phi(i32 %arg) {
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bb:
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%tidig = call i32 @llvm.amdgcn.workitem.id.x()
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%cmp = trunc i32 %tidig to i1
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br i1 %cmp, label %bb2, label %bb3
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bb2: ; preds = %bb
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br label %bb3
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bb3: ; preds = %bb2, %bb
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%tmp = phi i1 [ true, %bb2 ], [ false, %bb ]
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br i1 %tmp, label %bb4, label %bb6
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bb4: ; preds = %bb3
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%val = load volatile i32, i32 addrspace(1)* undef
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%tmp5 = mul i32 %val, %arg
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br label %bb6
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bb6: ; preds = %bb4, %bb3
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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