forked from OSchip/llvm-project
114 lines
4.0 KiB
C++
114 lines
4.0 KiB
C++
// WebAssemblyMachineFunctionInfo.h-WebAssembly machine function info-*- C++ -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file declares WebAssembly-specific per-machine-function
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/// information.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMACHINEFUNCTIONINFO_H
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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/// This class is derived from MachineFunctionInfo and contains private
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/// WebAssembly-specific information for each MachineFunction.
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class WebAssemblyFunctionInfo final : public MachineFunctionInfo {
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MachineFunction &MF;
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std::vector<MVT> Params;
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/// A mapping from CodeGen vreg index to WebAssembly register number.
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std::vector<unsigned> WARegs;
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/// A mapping from CodeGen vreg index to a boolean value indicating whether
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/// the given register is considered to be "stackified", meaning it has been
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/// determined or made to meet the stack requirements:
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/// - single use (per path)
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/// - single def (per path)
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/// - defined and used in LIFO order with other stack registers
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BitVector VRegStackified;
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// One entry for each possible target reg. we expect it to be small.
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std::vector<unsigned> PhysRegs;
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// A virtual register holding the pointer to the vararg buffer for vararg
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// functions. It is created and set in TLI::LowerFormalArguments and read by
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// TLI::LowerVASTART
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unsigned VarargVreg = -1U;
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public:
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explicit WebAssemblyFunctionInfo(MachineFunction &MF) : MF(MF) {
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PhysRegs.resize(WebAssembly::NUM_TARGET_REGS, -1U);
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}
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~WebAssemblyFunctionInfo() override;
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void addParam(MVT VT) { Params.push_back(VT); }
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const std::vector<MVT> &getParams() const { return Params; }
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unsigned getVarargBufferVreg() const {
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assert(VarargVreg != -1U && "Vararg vreg hasn't been set");
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return VarargVreg;
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}
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void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; }
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static const unsigned UnusedReg = -1u;
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void stackifyVReg(unsigned VReg) {
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if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
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VRegStackified.resize(TargetRegisterInfo::virtReg2Index(VReg) + 1);
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VRegStackified.set(TargetRegisterInfo::virtReg2Index(VReg));
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}
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void unstackifyVReg(unsigned VReg) {
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if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
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return;
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VRegStackified.reset(TargetRegisterInfo::virtReg2Index(VReg));
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}
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bool isVRegStackified(unsigned VReg) const {
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if (TargetRegisterInfo::virtReg2Index(VReg) >= VRegStackified.size())
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return false;
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return VRegStackified.test(TargetRegisterInfo::virtReg2Index(VReg));
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}
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void initWARegs();
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void setWAReg(unsigned VReg, unsigned WAReg) {
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assert(WAReg != UnusedReg);
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assert(TargetRegisterInfo::virtReg2Index(VReg) < WARegs.size());
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WARegs[TargetRegisterInfo::virtReg2Index(VReg)] = WAReg;
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}
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unsigned getWAReg(unsigned Reg) const {
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size());
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return WARegs[TargetRegisterInfo::virtReg2Index(Reg)];
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}
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return PhysRegs[Reg];
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}
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// If new virtual registers are created after initWARegs has been called,
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// this function can be used to add WebAssembly register mappings for them.
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void addWAReg(unsigned VReg, unsigned WAReg) {
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assert(VReg = WARegs.size());
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WARegs.push_back(WAReg);
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}
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void addPReg(unsigned PReg, unsigned WAReg) {
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assert(PReg < WebAssembly::NUM_TARGET_REGS);
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assert(WAReg < -1U);
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PhysRegs[PReg] = WAReg;
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}
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const std::vector<unsigned> &getPhysRegs() const { return PhysRegs; }
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};
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} // end namespace llvm
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#endif
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