forked from OSchip/llvm-project
21 lines
650 B
TableGen
21 lines
650 B
TableGen
// RUN: not llvm-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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def FakeTarget : Target { }
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def FakeModel : SchedMachineModel { }
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def WriteA : SchedWrite;
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def WriteB : SchedWrite;
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let SchedModel = NoSchedModel in {
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def : InstRW<[WriteA], (instrs COPY)>;
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def : InstRW<[WriteB], (instrs COPY)>;
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// CHECK: [[@LINE-1]]:3: error: Overlapping InstRW definition for "COPY" also matches previous "(instrs COPY)".
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// CHECK-NEXT: def : InstRW<[WriteB], (instrs COPY)>;
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// CHECK: [[@LINE-6]]:3: note: Previous match was here.
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// CHECK-NEXT: def : InstRW<[WriteA], (instrs COPY)>;
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} |