llvm-project/llvm/lib/CodeGen
Cong Hou cb07d7016a Fix a bug in IfConversion.cpp.
The bug is introduced in r254377 which failed some tests on ARM, where a new
probability is assigned to a successor but the provided BB may not be a
successor.

llvm-svn: 254463
2015-12-01 21:50:20 +00:00
..
AsmPrinter [DIE] Make DIE.h NDEBUG conditional-free. 2015-11-24 02:21:43 +00:00
MIRParser Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
SelectionDAG Fixed a failure in cost calculation for vector GEP 2015-12-01 12:08:36 +00:00
AggressiveAntiDepBreaker.cpp Revert "Simplify code. NFC." 2015-10-09 19:48:48 +00:00
AggressiveAntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
AllocationOrder.cpp TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
AllocationOrder.h TargetRegisterInfo: Provide a way to check assigned registers in getRegAllocationHints() 2015-07-15 22:16:00 +00:00
Analysis.cpp Remove assert(false) in favor of asserting the if conditional it is contained within. 2015-10-26 18:41:13 +00:00
AntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
AtomicExpandPass.cpp CodeGen: Start removing implicit conversions to/from list iterators, NFC 2015-10-09 16:54:49 +00:00
BasicTargetTransformInfo.cpp constify the Function parameter to the TTI creation callback and 2015-09-16 23:38:13 +00:00
BranchFolding.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
BranchFolding.h [WinEH] Permit branch folding in the face of funclets 2015-10-04 02:22:52 +00:00
CMakeLists.txt [WinEH] Add a funclet layout pass 2015-09-17 20:45:18 +00:00
CalcSpillWeights.cpp Trace copies when checking for rematerializability in spill weight calculation 2015-08-10 11:59:44 +00:00
CallingConvLower.cpp Arguments spilled on the stack before a function call may have 2015-09-29 10:12:57 +00:00
CodeGen.cpp [WinEH] Add a funclet layout pass 2015-09-17 20:45:18 +00:00
CodeGenPrepare.cpp [WinEH] Fix problem where CodeGenPrepare incorrectly sinks a bitcast into an EH pad. 2015-11-23 19:16:15 +00:00
CoreCLRGC.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
CriticalAntiDepBreaker.cpp MachineBasicBlock: Factor out common code into isReturnBlock() 2015-09-25 21:25:19 +00:00
CriticalAntiDepBreaker.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
DFAPacketizer.cpp Avoid dependency between TableGen and CodeGen 2015-11-22 15:20:19 +00:00
DeadMachineInstructionElim.cpp Save LaneMask with livein registers 2015-09-09 18:08:03 +00:00
DwarfEHPrepare.cpp [WinEH] Recognize CoreCLR personality function 2015-10-06 20:28:16 +00:00
EarlyIfConversion.cpp Avoid redundant select node in early if-conversion pass 2015-06-18 22:34:09 +00:00
EdgeBundles.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
ErlangGC.cpp
ExecutionDepsFix.cpp CodeGen: Start removing implicit conversions to/from list iterators, NFC 2015-10-09 16:54:49 +00:00
ExpandISelPseudos.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
ExpandPostRAPseudos.cpp
FaultMaps.cpp Revert "[FaultMaps] Move FaultMapParser to Object/" 2015-06-23 20:09:03 +00:00
FuncletLayout.cpp [WinEH] Update CATCHRET's operand to match its successor 2015-10-05 20:09:16 +00:00
GCMetadata.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
GCMetadataPrinter.cpp
GCRootLowering.cpp CodeGen: Remove a few more ilist iterator implicit conversions, NFC 2015-10-09 18:44:40 +00:00
GCStrategy.cpp
GlobalMerge.cpp CodeGen: Use range-based for in GlobalMerge, NFC 2015-10-09 18:57:47 +00:00
IfConversion.cpp Fix a bug in IfConversion.cpp. 2015-12-01 21:50:20 +00:00
ImplicitNullChecks.cpp [ImplicitNulls] Add some clarifying comments; NFC 2015-11-13 08:14:00 +00:00
InlineSpiller.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
InterferenceCache.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
InterferenceCache.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
InterleavedAccessPass.cpp [ARM][AArch64] Turn on by default interleaved access lowering 2015-09-01 11:12:35 +00:00
IntrinsicLowering.cpp Introduce new @llvm.get.dynamic.area.offset.i{32, 64} intrinsics. 2015-12-01 11:40:55 +00:00
LLVMBuild.txt LLVMCodeGen: Update libdeps corresponding to r246236. 2015-08-28 05:38:49 +00:00
LLVMTargetMachine.cpp Have 'optnone' respect the -fast-isel=false option. 2015-11-30 21:56:16 +00:00
LatencyPriorityQueue.cpp
LexicalScopes.cpp IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
LiveDebugVariables.cpp DI: Reverse direction of subprogram -> function edge. 2015-11-05 22:03:56 +00:00
LiveDebugVariables.h Erase unused FunctionDIs variables after r252219. 2015-11-07 10:21:25 +00:00
LiveInterval.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveIntervalAnalysis.cpp MachineInstr: addRegisterDefReadUndef() => setRegisterDefReadUndef() 2015-11-11 00:41:58 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp LivePhysRegs: Fix live-outs of return blocks 2015-09-25 23:50:53 +00:00
LiveRangeCalc.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRangeCalc.h TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRangeEdit.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
LiveRegMatrix.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp LiveVariables should not clobber MachineOperand::IsDead, ::IsKill on reserved physical registers 2015-11-24 20:06:56 +00:00
LocalStackSlotAllocation.cpp CodeGen: Remove more ilist iterator implicit conversions, NFC 2015-10-09 19:13:58 +00:00
MIRPrinter.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
MIRPrinter.h MIR Serialization: move the MIR printer out of the MIR printing pass. 2015-06-15 23:52:35 +00:00
MIRPrintingPass.cpp Re-commit r247216: "Fix Clang-tidy misc-use-override warnings, other minor fixes" 2015-09-10 16:49:58 +00:00
MachineBasicBlock.cpp Allow known and unknown probabilities coexist in MBB's successor list. 2015-12-01 11:05:39 +00:00
MachineBlockFrequencyInfo.cpp CodeGen: Avoid ilist iterator implicit conversions in a few more places, NFC 2015-10-09 19:23:20 +00:00
MachineBlockPlacement.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
MachineBranchProbabilityInfo.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
MachineCSE.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
MachineCombiner.cpp less indent; NFCI 2015-11-10 20:09:02 +00:00
MachineCopyPropagation.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp Remove macro guards for extern template instantiations. 2015-07-13 17:21:31 +00:00
MachineFunction.cpp Expand subregisters in MachineFrameInfo::getPristineRegs 2015-11-19 21:18:52 +00:00
MachineFunctionAnalysis.cpp MIR Serialization: Connect the machine function analysis pass to the MIR parser. 2015-06-15 20:30:22 +00:00
MachineFunctionPass.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
MachineFunctionPrinterPass.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
MachineInstr.cpp MachineInstr: addRegisterDefReadUndef() => setRegisterDefReadUndef() 2015-11-11 00:41:58 +00:00
MachineInstrBundle.cpp x86: Emit LAHF/SAHF instead of PUSHF/POPF 2015-08-10 20:59:36 +00:00
MachineLICM.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineLoopInfo.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
MachineModuleInfo.cpp [WinEH] Move WinEHFuncInfo from MachineModuleInfo to MachineFunction 2015-11-17 21:10:25 +00:00
MachineModuleInfoImpls.cpp Clear the stub map in getSortedStubs. 2015-04-07 12:59:28 +00:00
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
MachineSSAUpdater.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
MachineScheduler.cpp MachineScheduler: Print initial pressure in debug dump 2015-11-13 22:30:31 +00:00
MachineSink.cpp Refine the definition of convergent to only disallow the addition of new control dependencies. 2015-10-09 18:06:13 +00:00
MachineTraceMetrics.cpp fix crash in machine trace metrics due to processing dbg_value instructions (PR24199) 2015-07-23 22:56:53 +00:00
MachineVerifier.cpp MachineVerifier: Streamline live interval related error reporting 2015-11-09 23:59:33 +00:00
Makefile Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
OcamlGC.cpp
OptimizePHIs.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
PHIElimination.cpp [WinEH] Add some support for code generating catchpad 2015-08-27 23:27:47 +00:00
PHIEliminationUtils.cpp [WinEH] Add some support for code generating catchpad 2015-08-27 23:27:47 +00:00
PHIEliminationUtils.h
ParallelCG.cpp [LTO] Add option to emit assembly from LTOCodeGenerator 2015-11-19 23:59:24 +00:00
Passes.cpp Enable verifier after PeepholeOptimizer 2015-10-12 17:43:56 +00:00
PeepholeOptimizer.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
PostRASchedulerList.cpp MachineScheduler: Add regpressure information to debug dump 2015-11-06 20:59:02 +00:00
ProcessImplicitDefs.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
PrologEpilogInserter.cpp Support for emitting inline stack probes 2015-11-10 01:50:49 +00:00
PseudoSourceValue.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegAllocFast.cpp Save LaneMask with livein registers 2015-09-09 18:08:03 +00:00
RegAllocGreedy.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegAllocPBQP.cpp [PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible 2015-09-09 17:55:00 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp Assume lane masks are always precise 2015-11-17 00:50:55 +00:00
RegisterCoalescer.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
RegisterPressure.cpp RegisterPressure: If we do not collect dead defs the list must be empty 2015-12-01 04:20:06 +00:00
RegisterScavenging.cpp TargetRegisterInfo: Add typedef unsigned LaneBitmask and use it where apropriate; NFC 2015-09-25 21:51:14 +00:00
ScheduleDAG.cpp MachineScheduler: Add regpressure information to debug dump 2015-11-06 20:59:02 +00:00
ScheduleDAGInstrs.cpp ScheduleDAGInstrs: Remove IsPostRA flag; NFC 2015-11-03 01:53:29 +00:00
ScheduleDAGPrinter.cpp Make the SelectionDAG graph printer use SDNode::PersistentId labels. 2015-10-27 23:09:03 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShadowStackGCLowering.cpp CodeGen: Avoid more ilist iterator implicit conversions, NFC 2015-10-09 21:08:19 +00:00
ShrinkWrap.cpp [ShrinkWrap] Teach ShrinkWrap to handle targets requiring a register scavenger. 2015-11-20 21:54:27 +00:00
SjLjEHPrepare.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SlotIndexes.cpp CodeGen: Continue removing ilist iterator implicit conversions 2015-10-09 19:40:45 +00:00
SpillPlacement.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SpillPlacement.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
Spiller.h Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
SplitKit.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
SplitKit.h [CodeGen] Reduce visibility of implementation details 2015-07-01 14:47:39 +00:00
StackColoring.cpp Remove MCInstrItineraries includes in parts that don't use them anymore 2015-05-14 18:01:11 +00:00
StackMapLivenessAnalysis.cpp [StackMap Liveness] Calling the base class' getAnalysisUsage method. NFCI. 2015-07-07 02:05:18 +00:00
StackMaps.cpp Move most user of TargetMachine::getDataLayout to the Module one 2015-07-16 06:11:10 +00:00
StackProtector.cpp Refactor: Simplify boolean conditional return statements in lib/CodeGen. 2015-10-24 23:11:13 +00:00
StackSlotColoring.cpp PseudoSourceValue: Replace global manager with a manager in a machine function. 2015-08-11 23:09:45 +00:00
StatepointExampleGC.cpp Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC) 2015-06-23 09:49:53 +00:00
TailDuplication.cpp Replace all weight-based interfaces in MBB with probability-based interfaces, and update all uses of old interfaces. 2015-12-01 05:29:22 +00:00
TargetFrameLoweringImpl.cpp HHVM calling conventions. 2015-09-29 22:09:16 +00:00
TargetInstrInfo.cpp replace MachineCombinerPattern namespace and enum with enum class; NFCI 2015-11-05 19:34:57 +00:00
TargetLoweringBase.cpp Introduce new @llvm.get.dynamic.area.offset.i{32, 64} intrinsics. 2015-12-01 11:40:55 +00:00
TargetLoweringObjectFileImpl.cpp Stop producing .data.rel sections. 2015-11-18 06:02:15 +00:00
TargetOptionsImpl.cpp Use function attribute "trap-func-name" and remove TargetOptions::TrapFuncName. 2015-07-02 22:13:27 +00:00
TargetRegisterInfo.cpp TargetRegisterInfo: Introduce PrintLaneMask. 2015-09-25 21:51:24 +00:00
TargetSchedule.cpp Use llvm_unreachable() instead of report_fatal_error() if the machine model is incomplete 2015-07-17 17:50:11 +00:00
TwoAddressInstructionPass.cpp use range-based for loops; NFCI 2015-12-01 19:57:43 +00:00
UnreachableBlockElim.cpp CodeGen: Remove implicit ilist iterator conversions, NFC 2015-10-09 22:56:24 +00:00
VirtRegMap.cpp Assume lane masks are always precise 2015-11-17 00:50:55 +00:00
WinEHPrepare.cpp [WinEH] Disable most forms of demotion 2015-11-19 23:23:33 +00:00
module.modulemap

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.