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llvm-project/llvm/test/CodeGen
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Danila Malyutin 940ba1465b Fix possible assertion when using PBQP with debug info 
Skip debug instructions before calling functions not expecting them.
In particular, LIS.getInstructionIndex(*mi) would fail if mi was a debg instr.

Differential Revision: https://reviews.llvm.org/D76129
 		2020-03-18 15:29:42 +03:00
..
AArch64 Revert "Support repeated machine outlining" 2020-03-17 18:33:55 -07:00
AMDGPU Revert "AMDGPU/GlobalISel: Fully handle 0 dmask case during legalize" 2020-03-17 22:04:14 -07:00
ARC
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ARM [CodeGenPrepare] Freeze condition when transforming select to br 2020-03-16 12:46:20 +09:00
AVR [AVR] Fix incorrect register state for LDRdPtr 2020-03-03 17:34:54 +08:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Generic Fix possible assertion when using PBQP with debug info 2020-03-18 15:29:42 +03:00
Hexagon [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Inputs
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Lanai Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
MIR Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" 2020-03-13 15:37:44 -04:00
MSP430
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Mips [GlobalISel] combine G_TRUNC with G_MERGE_VALUES 2020-03-16 14:42:01 +01:00
NVPTX ARM: Fixup some tests using denormal-fp-math attribute 2020-03-10 14:02:06 -04:00
PowerPC [DAGCombine] Respect the uses when combine FMA for a*b+/-c*d 2020-03-18 03:34:27 +00:00
RISCV [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
SPARC [Sparc] Fix incorrect operand for matching CMPri pattern 2020-03-02 11:36:32 +08:00
SystemZ [TargetLowering] Only demand a rotation's modulo amount bits 2020-03-17 21:23:46 +00:00
Thumb [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Thumb2 [ARM,MVE] Add intrinsics for the VQDMLAH family. 2020-03-18 10:55:04 +00:00
VE [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
WebAssembly [WebAssembly] Fix SIMD shift unrolling to avoid assertion failure 2020-03-12 12:20:14 -07:00
WinCFGuard
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WinEH
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X86 CET for Exception Handle 2020-03-17 22:35:05 -07:00
XCore [XCore] Add instruction pattern for bitrev 2020-02-21 09:28:49 +08:00