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llvm-project/llvm/test/MC/AMDGPU
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Matt Arsenault 9dba9bd4cf AMDGPU: Use source modifiers with f16->f32 conversions 
The operand types were defined to fit the fp16_to_fp node, which
has the half as an integer type. v_cvt_f32_f16 does support
source modifiers, so change this to have an FP type and modifiers.

For targets without legal f16, this requires recognizing the
bit operations and trying to produce them.

llvm-svn: 293857
 		2017-02-02 02:27:04 +00:00
..
regression [AMDGPU][mc] Add regression tests for Bug 28168 2016-09-20 11:58:40 +00:00
buffer_wbinv1l_vol_vi.s
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ds-err.s [AMDGPU] Assembler: rework parsing of optional operands. 2016-05-24 12:38:33 +00:00
ds.s [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed. 2016-10-21 14:49:22 +00:00
exp-err.s AMDGPU: Assembler support for exp 2016-12-05 20:42:41 +00:00
exp.s AMDGPU: Fix assembler encoding for EXP instructions on VI 2017-01-30 12:25:03 +00:00
expressions.s AMDGPU/SI: Correctly encode constant expressions 2016-06-15 03:09:39 +00:00
flat-scratch.s [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms. 2016-05-23 09:59:02 +00:00
flat.s
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gfx8_asm_all.s AMDGPU: Use source modifiers with f16->f32 conversions 2017-02-02 02:27:04 +00:00
hsa-exp.s AMDGPU: Set call_convention bit in kernel_code_t 2017-01-25 20:21:57 +00:00
hsa-text.s AMDGPU/SI: Add support for AMD code object version 2. 2016-05-05 17:03:33 +00:00
hsa.s AMDGPU: Set call_convention bit in kernel_code_t 2017-01-25 20:21:57 +00:00
hsa_code_object_isa_args.s [AMDGPU][mc] Enable absolute expressions in .hsa_code_object_isa directive 2016-12-29 15:41:52 +00:00
labels-branch.s [AMDGPU] Disassembler: print label names in branch instructions 2016-10-06 13:46:08 +00:00
lit.local.cfg
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literal16-err.s AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
literal16.s AMDGPU: Fix handling of 16-bit immediates 2016-12-10 00:39:12 +00:00
literals.s AMDGPU: Fix formatting of 1/2pi immediate 2016-11-15 00:04:33 +00:00
macro-examples.s [test/AMDGPU] Square-braced-syntax for registers: add macro test/example. 2016-06-03 14:41:17 +00:00
max-branch-distance.s AMDGPU: Improve error reporting for maximum branch distance 2016-08-27 00:21:22 +00:00
metadata.s AMDGPU: [AMDGPU] Assembler: add .hsa_code_object_metadata directive for functime metadata V2.0 2016-12-19 11:43:15 +00:00
mimg.s
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mubuf.s [AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3. 2016-10-07 15:53:16 +00:00
out-of-range-registers.s [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms. 2016-05-23 09:59:02 +00:00
reg-syntax-extra.s AMDGPU] Assembler: better support for immediate literals in assembler. 2016-09-09 14:44:04 +00:00
reloc.s [AMDGPU] Add 32-bit lo/hi got and pc relative variant kinds and emit appropriate relocations 2016-10-14 04:21:32 +00:00
smem-err.s AMDGPU: Disallow exec as SMEM instruction operand 2016-11-29 19:39:53 +00:00
smem.s AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions 2016-12-09 17:49:11 +00:00
smrd-err.s AMDGPU: Add definitions for scalar store instructions 2016-10-28 21:55:15 +00:00
smrd.s AMDGPU: Allow TBA, TMA, TTMP* registers with SMEM instructions 2016-12-09 17:49:11 +00:00
sop1-err.s AMDGPU] Assembler: better support for immediate literals in assembler. 2016-09-09 14:44:04 +00:00
sop1.s AMDGPU: Add instruction definitions for VGPR indexing 2016-10-12 18:00:51 +00:00
sop2.s [AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms. 2016-05-23 09:59:02 +00:00
sopc-err.s AMDGPU: Add instruction definitions for VGPR indexing 2016-10-12 18:00:51 +00:00
sopc.s AMDGPU: Add instruction definitions for VGPR indexing 2016-10-12 18:00:51 +00:00
sopk-err.s [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 2016-04-27 15:17:03 +00:00
sopk.s [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 2016-04-27 15:17:03 +00:00
sopp-err.s [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc. 2016-05-26 17:00:33 +00:00
sopp.s AMDGPU: Add instruction definitions for VGPR indexing 2016-10-12 18:00:51 +00:00
sym_kernel_scope.s [AMDGPU][llvm-mc] Predefined symbols to access register counts (.kernel.{v|s}gpr_count) 2016-12-27 16:00:11 +00:00
sym_option.s [AMDGPU][llvm-mc] Predefined symbols to access register counts (.kernel.{v|s}gpr_count) 2016-12-27 16:00:11 +00:00
trap.s AMDGPU] Assembler: better support for immediate literals in assembler. 2016-09-09 14:44:04 +00:00
vintrp-err.s AMDGPU: Assembler support for vintrp instructions 2016-12-15 20:40:20 +00:00
vintrp.s AMDGPU: Assembler support for vintrp instructions 2016-12-15 20:40:20 +00:00
vop1.s AMDGPU] Assembler: better support for immediate literals in assembler. 2016-09-09 14:44:04 +00:00
vop2-err.s [AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC. 2016-06-06 15:23:43 +00:00
vop2.s AMDGPU: Fix name for v_ashrrev_i16 2016-12-16 17:40:11 +00:00
vop3-convert.s AMDGPU: Fix name for v_ashrrev_i16 2016-12-16 17:40:11 +00:00
vop3-errs.s AMDGPU : Fix mqsad_u32_u8 instruction incorrect data type. 2016-09-09 19:31:51 +00:00
vop3-vop1-nosrc.s
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vop3.s AMDGPU: Remove modifiers from v_div_scale_* 2017-01-19 06:04:12 +00:00
vop_dpp.s [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate operands 2017-01-11 11:46:30 +00:00
vop_dpp_expr.s [AMDGPU][mc] Add support for absolute expressions in DPP modifiers. 2016-09-22 11:47:21 +00:00
vop_sdwa.s [AMDGPU] Assembler: SDWA/DPP should not accept scalar registers and immediate operands 2017-01-11 11:46:30 +00:00
vopc-errs.s
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vopc-vi.s AMDGPU: Fix missing 16-bit cmpx instructions 2016-12-22 16:27:14 +00:00
vopc.s
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