llvm-project/llvm/test/CodeGen
Francis Visoiu Mistrih 93ef145862 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
2017-11-30 12:12:19 +00:00
..
AArch64 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
AMDGPU [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
ARC
ARM [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
AVR [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
BPF [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
Generic Support generic lowering of vector bswap 2017-11-30 11:06:22 +00:00
Hexagon [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
Inputs
Lanai [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
MIR [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
MSP430
Mips [CodeGen] Print register names in lowercase in both MIR and debug output 2017-11-28 17:15:09 +00:00
NVPTX [NVPTX] Implement __nvvm_atom_add_gen_d builtin. 2017-11-07 22:10:54 +00:00
Nios2
PowerPC [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
RISCV [RISCV] Use register X0 (ZERO) for constant 0 2017-11-21 08:23:08 +00:00
SPARC [Sparc] efficient pattern for UINT_TO_FP conversion 2017-11-20 22:33:58 +00:00
SystemZ [SystemZ] Bugfix in adjustSubwordCmp. 2017-11-30 08:18:50 +00:00
Thumb [ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb 2017-11-27 10:13:14 +00:00
Thumb2 [arm] Fix Unnecessary reloads from GOT. 2017-11-13 20:45:38 +00:00
WebAssembly [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
XCore [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00