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llvm-project/llvm/lib/CodeGen/MIRParser
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Ahmed Bougacha bf480554df [MIRParser] Allow generic register specification on operand. 
This completes r292321 by adding support for generic registers, e.g.:

  %2:_(s32) = G_ADD %0, %1

llvm-svn: 292550
 		2017-01-20 00:29:59 +00:00
..
CMakeLists.txt [CMake] NFC. Updating CMake dependency specifications 2016-11-17 04:36:50 +00:00
LLVMBuild.txt MIRParser/LLVMBuild.txt: Add MC for MCRegisterInfo::getDwarfRegNum(). 2015-07-24 01:12:36 +00:00
MILexer.cpp [MIRParser] Parse lane masks for register live-ins 2016-10-12 21:06:45 +00:00
MILexer.h [MIRParser] Parse lane masks for register live-ins 2016-10-12 21:06:45 +00:00
MIParser.cpp [MIRParser] Allow generic register specification on operand. 2017-01-20 00:29:59 +00:00
MIParser.h MIRParser: Allow regclass specification on operand 2017-01-18 00:59:19 +00:00
MIRParser.cpp MIRParser: Allow regclass specification on operand 2017-01-18 00:59:19 +00:00