Stanislav Mekhanoshin 8a9d48b46d [AMDGPU] Fixed lane mask in test. NFC.		2020-04-15 15:26:53 -07:00
..
AArch64	[llvm][CodeGen] Rename SVE gather prefetch intrinsics. [NFC]	2020-04-15 21:49:16 +01:00
AMDGPU	[AMDGPU] Fixed lane mask in test. NFC.	2020-04-15 15:26:53 -07:00
ARC	…
ARM	Write ignored output to stdout, so this test runs on read-only filesystems.	2020-04-15 10:45:14 -07:00
AVR	[AVR] Generalize the previous interrupt bugfix to signal handlers too	2020-03-31 19:33:34 +13:00
BPF	[llvm] Fix missing FileCheck directive colons	2020-04-06 09:59:08 -06:00
Generic	[mir-strip-debug] Optionally preserve debug info that wasn't from debugify/mir-debugify	2020-04-10 15:24:14 -07:00
Hexagon	[Pipeliner] Fix the bug in pragma that disables the pipeliner.	2020-04-10 12:52:16 -05:00
Inputs	…
Lanai	…
MIR	AMDGPU: Assume f32 denormals are enabled by default	2020-04-02 17:17:12 -04:00
MSP430	…
Mips	[GlobalISel] Enable artifact combiner to combine starting from a G_MERGE_VALUES.	2020-04-15 10:34:13 -07:00
NVPTX	[llvm] Fix missing FileCheck directive colons	2020-04-06 09:59:08 -06:00
PowerPC	[AIX][PowerPC] Implement caller byval arguments in stack memory	2020-04-15 17:57:31 -04:00
RISCV	[SelectionDAG] Fix usage of Align constructing MachineMemOperands.	2020-04-15 13:01:41 -07:00
SPARC	[Sparc] Fix incorrect operand for matching CMPri pattern	2020-03-02 11:36:32 +08:00
SystemZ	[SystemZ] Bugfix in adjustSubwordCmp()	2020-04-15 12:58:39 +02:00
Thumb	[ARM] unwinding .pad instructions missing in execute-only prologue	2020-04-07 11:51:59 +01:00
Thumb2	[Target][ARM] Fix VPT Block Pass miscompilation	2020-04-14 15:16:27 +01:00
VE	[VE] Update integer arithmetic instructions	2020-04-15 09:47:51 +02:00
WebAssembly	[WebAssembly] Fix try placement in fixing unwind mismatches	2020-04-13 15:50:01 -07:00
WinCFGuard	…
WinEH	…
X86	[SelectionDAG] Fix usage of Align constructing MachineMemOperands.	2020-04-15 13:01:41 -07:00
XCore	…