llvm-project

History

Puyan Lotfi f63b64c0c3 [llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands. This patch makes it so that cases where multiple instructions that differ only in their ConstantInt or ConstantFP MachineOperand values no longer collide. For instance: %0:_(s1) = G_CONSTANT i1 true %1:_(s1) = G_CONSTANT i1 false %2:_(s32) = G_FCONSTANT float 1.0 %3:_(s32) = G_FCONSTANT float 0.0 Prior to this patch the first two instructions would collide together. Also, the last two G_FCONSTANT instructions would also collide. Now they will no longer collide. Differential Revision: https://reviews.llvm.org/D71558		2019-12-16 18:25:04 -05:00
..
AArch64	[MIRNamer]: Make the check lines in the test robust with regex.	2019-11-16 22:58:45 -08:00
AMDGPU	[llvm][MIRVRegNamerUtils] Adding hashing on memoperands.	2019-12-11 22:11:49 -05:00
ARM	Followup on Proposal to move MIR physical register namespace to '$' sigil.	2018-01-31 22:04:26 +00:00
Generic	[llvm][MIRVRegNamerUtils] Adding hashing on CImm / FPImm MachineOperands.	2019-12-16 18:25:04 -05:00
Hexagon	[DebugInfo] Allow bundled calls in the MIR's call site info	2019-08-19 12:41:22 +00:00
Mips	[MIParser] Set RegClassOrRegBank during instruction parsing	2019-10-22 14:25:37 +00:00
NVPTX	…
PowerPC	[PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC	2019-09-13 14:18:36 +00:00
WebAssembly	[WebAssembly] Fix tests missed in rL374235	2019-10-09 23:06:38 +00:00
X86	[llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.	2019-12-10 20:16:14 -05:00
README	…

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.