llvm-project/llvm/test/CodeGen
Craig Topper 8b53fdd3b6 [X86] Custom legalize v16i64->v16i8 truncate with avx512.
Default legalization will create two v8i64 truncs to v8i32, concat
them to v16i32, and then truncate the rest of the way to v16i8.

Instead we can truncate directly from v8i64 to v8i8 in the lower
half of an xmm. Then concat the two halves to use vpunpcklqdq.
This is the same number of uops, but the dependency chain through
the uops is better since the halves are merged at the end.

I had to had SimplifyDemandedBits support for VTRUNC to prevent
a regression on vector-trunc-math.ll. combineTruncatedArithmetic
no longer gets a chance to shrink vXi64 mul so we were producing
the v8i64 multiply sequence using multiple PMULUDQs. With the
demanded bits fix we are able to prune out the extra ops leaving
just two PMULUDQs, one for each v8i64 half. This is twice the
width of the 2 v8i32 PMULLDs we had before, but PMULUDQ is 1
uop and PMULLD is 2. We also save some truncates. It's probably
worth using PMULUDQ even when PMULLQ is available since the latter
is 3 uops, but that will require a different change.

Differential Revision: https://reviews.llvm.org/D79231
2020-05-03 23:26:04 -07:00
..
AArch64 [AArch64][SVE] Custom lowering of floating-point reductions 2020-04-30 10:18:40 +00:00
AMDGPU [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad 2020-05-02 15:18:10 -07:00
ARC
ARM [BPI][NFC] Reuse post dominantor tree from analysis manager when available 2020-04-30 11:31:03 +07:00
AVR [AVR] Do not place functions in .progmem.data 2020-04-20 13:56:38 +02:00
BPF BPF: fix a CORE optimization bug 2020-04-20 19:54:51 -07:00
Generic [MachineDebugify] Insert synthetic DBG_VALUE instructions 2020-04-22 17:03:39 -07:00
Hexagon Handle cases for subregisters. 2020-04-30 20:32:33 -05:00
Inputs
Lanai
MIR [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
MSP430
Mips [AsmPrinter] Fix emission of non-standard integer constants for BE targets 2020-04-27 14:57:29 -07:00
NVPTX [llvm] Fix missing FileCheck directive colons 2020-04-06 09:59:08 -06:00
PowerPC [AIX] emit .extern and .weak directive linkage 2020-04-30 09:54:10 -04:00
RISCV [RISCV] Implement convertSelectOfConstantsToMath 2020-05-02 15:05:57 +01:00
SPARC
SystemZ [SystemZ] Fix test case. 2020-04-28 09:43:03 +02:00
Thumb [ARM] Don't shrink STM if it would cause an unknown base register store 2020-04-22 14:50:42 +01:00
Thumb2 [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad 2020-05-02 15:18:10 -07:00
VE [VE] Update branch instructions 2020-04-28 09:41:01 +02:00
WebAssembly [WebAssembly] Renumber SIMD opcodes 2020-05-01 17:20:49 -07:00
WinCFGuard
WinEH
X86 [X86] Custom legalize v16i64->v16i8 truncate with avx512. 2020-05-03 23:26:04 -07:00
XCore