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Evgeniy Stepanov 99fa3e774d [hwasan] Stack instrumentation. 
Summary:
Very basic stack instrumentation using tagged pointers.
Tag for N'th alloca in a function is built as XOR of:
 * base tag for the function, which is just some bits of SP (poor
   man's random)
 * small constant which is a function of N.

Allocas are aligned to 16 bytes. On every ReturnInst allocas are
re-tagged to catch use-after-return.

This implementation has a bunch of issues that will be taken care of
later:
1. lifetime intrinsics referring to tagged pointers are not
   recognized in SDAG. This effectively disables stack coloring.
2. Generated code is quite inefficient. There is one extra
   instruction at each memory access that adds the base tag to the
   untagged alloca address. It would be better to keep tagged SP in a
   callee-saved register and address allocas as an offset of that XOR
   retag, but that needs better coordination between hwasan
   instrumentation pass and prologue/epilogue insertion.
3. Lifetime instrinsics are ignored and use-after-scope is not
   implemented. This would be harder to do than in ASan, because we
   need to use a differently tagged pointer depending on which
   lifetime.start / lifetime.end the current instruction is dominated
   / post-dominated.

Reviewers: kcc, alekseyshl

Subscribers: srhines, kubamracek, javed.absar, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D41602

llvm-svn: 322324
 		2018-01-11 22:53:30 +00:00
..
AsmParser [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands 2018-01-10 10:10:56 +00:00
Disassembler Recommit r322073: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions 2018-01-09 17:01:27 +00:00
InstPrinter [AArch64][SVE] Asm: Add SVE (Z) Register definitions and parsing support 2017-11-07 16:45:48 +00:00
MCTargetDesc Thread MCSubtargetInfo through Target::createMCAsmBackend 2018-01-03 08:53:05 +00:00
TargetInfo Add backend name to Target to enable runtime info to be fed back into TableGen 2017-11-15 23:55:44 +00:00
Utils [AArch64] Add support for dllimport of values and functions 2017-10-25 07:25:18 +00:00
AArch64.h [AArch64] Avoid SIMD interleaved store instruction for Exynos. 2017-12-08 00:58:49 +00:00
AArch64.td [AArch64][SVE] Asm: Add parsing of merging/zeroing suffix for SVE predicate vector operands 2018-01-09 11:17:06 +00:00
AArch64A53Fix835769.cpp Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64A57FPLoadBalancing.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64AdvSIMDScalarPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64AsmPrinter.cpp AArch64: fix one more place movi.2d could be created. 2017-12-20 10:45:39 +00:00
AArch64CallLowering.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CallLowering.h GlobalISel (AArch64): fix ABI at border between GPRs and SP. 2017-08-21 21:56:11 +00:00
AArch64CallingConvention.h Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering 2017-11-08 01:01:31 +00:00
AArch64CallingConvention.td AArch64: support SwiftCC properly on AAPCS64 2017-09-22 04:31:44 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CollectLOH.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64CondBrTuning.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionOptimizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ConditionalCompares.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64DeadRegisterDefinitionsPass.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ExpandPseudoInsts.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64FalkorHWPFFix.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64FastISel.cpp Silence a bunch of implicit fallthrough warnings 2017-12-19 22:05:25 +00:00
AArch64FrameLowering.cpp Revert "AArch64: Fix emergency spillslot being out of reach for large callframes" 2018-01-10 22:36:28 +00:00
AArch64FrameLowering.h Move TargetFrameLowering.h to CodeGen where it's implemented 2017-11-03 22:32:11 +00:00
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies 2017-11-18 04:28:56 +00:00
AArch64ISelDAGToDAG.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64ISelLowering.cpp Revert "AArch64: Fix emergency spillslot being out of reach for large callframes" 2018-01-10 22:36:28 +00:00
AArch64ISelLowering.h [hwasan] Stack instrumentation. 2018-01-11 22:53:30 +00:00
AArch64InstrAtomics.td [globalisel][tablegen] Add support for relative AtomicOrderings 2017-11-30 21:05:59 +00:00
AArch64InstrFormats.td [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero. 2017-10-23 18:19:24 +00:00
AArch64InstrInfo.cpp [MachineOutliner] Outline ADRPs 2018-01-10 18:49:57 +00:00
AArch64InstrInfo.h [MachineOutliner] AArch64: Handle instrs that use SP and will never need fixups 2018-01-09 00:26:18 +00:00
AArch64InstrInfo.td [AArch64] Improve code generation of vector build 2018-01-04 21:43:12 +00:00
AArch64InstructionSelector.cpp Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. 2017-12-05 05:52:07 +00:00
AArch64LegalizerInfo.cpp Revert r319691: [globalisel][tablegen] Split atomic load/store into separate opcode and enable for AArch64. 2017-12-05 05:52:07 +00:00
AArch64LegalizerInfo.h [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal 2017-11-28 20:21:15 +00:00
AArch64LoadStoreOptimizer.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64MCInstLower.cpp Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64MCInstLower.h [COFF, ARM64] Add support for Windows ARM64 COFF format 2017-06-27 23:58:19 +00:00
AArch64MachineFunctionInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64MacroFusion.cpp Remove redundant includes from lib/Target/AArch64. 2017-12-14 10:36:20 +00:00
AArch64MacroFusion.h Recommit rL305677: [CodeGen] Add generic MacroFusion pass 2017-06-19 12:53:31 +00:00
AArch64PBQPRegAlloc.cpp Rename LiveIntervalAnalysis.h to LiveIntervals.h 2017-12-13 02:51:04 +00:00
AArch64PBQPRegAlloc.h [CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-06-01 23:25:02 +00:00
AArch64PerfectShuffle.h
…
AArch64PromoteConstant.cpp [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
AArch64RedundantCopyElimination.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64RegisterBankInfo.cpp [AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR 2017-11-18 04:28:59 +00:00
AArch64RegisterBankInfo.h [AArch64][RegisterBankInfo] Add mapping for G_FPEXT. 2017-11-02 23:38:19 +00:00
AArch64RegisterBanks.td [aarch64][globalisel] Register banks and classes should have distinct names. 2017-10-18 00:12:43 +00:00
AArch64RegisterInfo.cpp Revert "AArch64: Fix emergency spillslot being out of reach for large callframes" 2018-01-10 22:36:28 +00:00
AArch64RegisterInfo.h AArch64: Enable post-ra liveness updates 2016-12-16 23:55:43 +00:00
AArch64RegisterInfo.td [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors. 2018-01-03 10:15:46 +00:00
AArch64SIMDInstrOpt.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64SVEInstrInfo.td [AArch64][SVE] Asm: Add support for (mov|dup) of scalar 2018-01-10 11:32:47 +00:00
AArch64SchedA53.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedA57WriteRes.td [AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit) 2016-12-23 12:51:41 +00:00
AArch64SchedCyclone.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedFalkor.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedFalkorDetails.td [AArch64][Falkor] Remove some non-existent opcodes from sched detail regexes. NFC. 2017-06-23 21:59:09 +00:00
AArch64SchedKryo.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedKryoDetails.td [AArch64][Kryo] Add missing write latency for LDAXP, LDXP second destination. 2017-06-19 21:57:42 +00:00
AArch64SchedM1.td [AArch64] Adjust the cost model for Exynos M1 and M2 2017-11-22 22:48:50 +00:00
AArch64SchedThunderX.td [AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models. 2017-11-07 15:03:11 +00:00
AArch64SchedThunderX2T99.td [AArch64] Remove Unsupported = 1 flag for the WriteAtomic WriteRes. 2018-01-11 16:50:56 +00:00
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp AArch64/X86: Factor out common bzero logic; NFC 2017-12-18 23:14:28 +00:00
AArch64SelectionDAGInfo.h
…
AArch64StorePairSuppress.cpp MachineFunction: Return reference from getFunction(); NFC 2017-12-15 22:22:58 +00:00
AArch64Subtarget.cpp Revert "AArch64: Fix emergency spillslot being out of reach for large callframes" 2018-01-10 22:36:28 +00:00
AArch64Subtarget.h Revert "AArch64: Fix emergency spillslot being out of reach for large callframes" 2018-01-10 22:36:28 +00:00
AArch64SystemOperands.td [AArch64] CCSIDR2 system register 2017-12-20 08:56:41 +00:00
AArch64TargetMachine.cpp [AArch64][GlobalISel] Enable GlobalISel at -O0 by default 2018-01-02 16:30:47 +00:00
AArch64TargetMachine.h (Re-landing) Expose a TargetMachine::getTargetTransformInfo function 2017-12-22 18:21:59 +00:00
AArch64TargetObjectFile.cpp Move Object format code to lib/BinaryFormat. 2017-06-07 03:48:56 +00:00
AArch64TargetObjectFile.h Fix a bunch more layering of CodeGen headers that are in Target 2017-11-17 01:07:10 +00:00
AArch64TargetTransformInfo.cpp Fix -Wsign-compare warnings on Windows 2018-01-05 19:53:51 +00:00
AArch64TargetTransformInfo.h [AArch64] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). 2017-07-25 23:51:02 +00:00
CMakeLists.txt [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features. 2017-12-08 22:04:13 +00:00
LLVMBuild.txt
…
SVEInstrFormats.td [AArch64][SVE] Asm: Add support for (mov|dup) of scalar 2018-01-10 11:32:47 +00:00