forked from OSchip/llvm-project
733 lines
43 KiB
TableGen
733 lines
43 KiB
TableGen
//=- AArch64SVEInstrInfo.td - AArch64 SVE Instructions -*- tablegen -*-----=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// AArch64 Scalable Vector Extension (SVE) Instruction definitions.
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//
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//===----------------------------------------------------------------------===//
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let Predicates = [HasSVE] in {
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defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
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defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
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defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">;
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defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">;
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defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
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defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
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def AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
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def ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
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def EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
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def BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
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defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
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defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">;
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defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">;
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defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">;
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defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
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defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">;
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defm SQADD_ZI : sve_int_arith_imm0<0b100, "sqadd">;
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defm UQADD_ZI : sve_int_arith_imm0<0b101, "uqadd">;
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defm SQSUB_ZI : sve_int_arith_imm0<0b110, "sqsub">;
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defm UQSUB_ZI : sve_int_arith_imm0<0b111, "uqsub">;
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defm ORR_ZI : sve_int_log_imm<0b00, "orr", "orn">;
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defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon">;
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defm AND_ZI : sve_int_log_imm<0b10, "and", "bic">;
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defm FADD_ZPmI : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
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defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
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defm FMAX_ZPmI : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
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// Splat immediate (unpredicated)
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defm DUP_ZI : sve_int_dup_imm<"dup">;
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defm FDUP_ZI : sve_int_dup_fpimm<"fdup">;
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defm DUPM_ZI : sve_int_dup_mask_imm<"dupm">;
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// Splat immediate (predicated)
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defm CPY_ZPmI : sve_int_dup_imm_pred_merge<"cpy">;
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defm CPY_ZPzI : sve_int_dup_imm_pred_zero<"cpy">;
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defm FCPY_ZPmI : sve_int_dup_fpimm_pred<"fcpy">;
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// Splat scalar register (unpredicated, GPR or vector + element index)
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defm DUP_ZR : sve_int_perm_dup_r<"dup">;
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defm DUP_ZZI : sve_int_perm_dup_i<"dup">;
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// Splat scalar register (predicated)
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defm CPY_ZPmR : sve_int_perm_cpy_r<"cpy">;
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defm CPY_ZPmV : sve_int_perm_cpy_v<"cpy">;
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// Select elements from either vector (predicated)
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defm SEL_ZPZZ : sve_int_sel_vvv<"sel">;
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def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
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def BIC_PPzPP : sve_int_pred_log<0b0001, "bic">;
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def EOR_PPzPP : sve_int_pred_log<0b0010, "eor">;
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def SEL_PPPP : sve_int_pred_log<0b0011, "sel">;
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def ANDS_PPzPP : sve_int_pred_log<0b0100, "ands">;
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def BICS_PPzPP : sve_int_pred_log<0b0101, "bics">;
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def EORS_PPzPP : sve_int_pred_log<0b0110, "eors">;
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def ORR_PPzPP : sve_int_pred_log<0b1000, "orr">;
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def ORN_PPzPP : sve_int_pred_log<0b1001, "orn">;
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def NOR_PPzPP : sve_int_pred_log<0b1010, "nor">;
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def NAND_PPzPP : sve_int_pred_log<0b1011, "nand">;
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def ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs">;
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def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">;
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def NORS_PPzPP : sve_int_pred_log<0b1110, "nors">;
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def NANDS_PPzPP : sve_int_pred_log<0b1111, "nands">;
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// continuous load with reg+immediate
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defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
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defm LD1B_H_IMM : sve_mem_cld_si<0b0001, "ld1b", Z_h, ZPR16>;
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defm LD1B_S_IMM : sve_mem_cld_si<0b0010, "ld1b", Z_s, ZPR32>;
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defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
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defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
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defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;
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defm LD1H_S_IMM : sve_mem_cld_si<0b0110, "ld1h", Z_s, ZPR32>;
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defm LD1H_D_IMM : sve_mem_cld_si<0b0111, "ld1h", Z_d, ZPR64>;
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defm LD1SH_D_IMM : sve_mem_cld_si<0b1000, "ld1sh", Z_d, ZPR64>;
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defm LD1SH_S_IMM : sve_mem_cld_si<0b1001, "ld1sh", Z_s, ZPR32>;
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defm LD1W_IMM : sve_mem_cld_si<0b1010, "ld1w", Z_s, ZPR32>;
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defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
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defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
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defm LD1SB_S_IMM : sve_mem_cld_si<0b1101, "ld1sb", Z_s, ZPR32>;
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defm LD1SB_H_IMM : sve_mem_cld_si<0b1110, "ld1sb", Z_h, ZPR16>;
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defm LD1D_IMM : sve_mem_cld_si<0b1111, "ld1d", Z_d, ZPR64>;
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// LD1R loads (splat scalar to vector)
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defm LD1RB_IMM : sve_mem_ld_dup<0b00, 0b00, "ld1rb", Z_b, ZPR8, uimm6s1>;
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defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
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defm LD1RB_S_IMM : sve_mem_ld_dup<0b00, 0b10, "ld1rb", Z_s, ZPR32, uimm6s1>;
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defm LD1RB_D_IMM : sve_mem_ld_dup<0b00, 0b11, "ld1rb", Z_d, ZPR64, uimm6s1>;
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defm LD1RSW_IMM : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>;
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defm LD1RH_IMM : sve_mem_ld_dup<0b01, 0b01, "ld1rh", Z_h, ZPR16, uimm6s2>;
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defm LD1RH_S_IMM : sve_mem_ld_dup<0b01, 0b10, "ld1rh", Z_s, ZPR32, uimm6s2>;
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defm LD1RH_D_IMM : sve_mem_ld_dup<0b01, 0b11, "ld1rh", Z_d, ZPR64, uimm6s2>;
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defm LD1RSH_D_IMM : sve_mem_ld_dup<0b10, 0b00, "ld1rsh", Z_d, ZPR64, uimm6s2>;
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defm LD1RSH_S_IMM : sve_mem_ld_dup<0b10, 0b01, "ld1rsh", Z_s, ZPR32, uimm6s2>;
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defm LD1RW_IMM : sve_mem_ld_dup<0b10, 0b10, "ld1rw", Z_s, ZPR32, uimm6s4>;
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defm LD1RW_D_IMM : sve_mem_ld_dup<0b10, 0b11, "ld1rw", Z_d, ZPR64, uimm6s4>;
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defm LD1RSB_D_IMM : sve_mem_ld_dup<0b11, 0b00, "ld1rsb", Z_d, ZPR64, uimm6s1>;
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defm LD1RSB_S_IMM : sve_mem_ld_dup<0b11, 0b01, "ld1rsb", Z_s, ZPR32, uimm6s1>;
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defm LD1RSB_H_IMM : sve_mem_ld_dup<0b11, 0b10, "ld1rsb", Z_h, ZPR16, uimm6s1>;
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defm LD1RD_IMM : sve_mem_ld_dup<0b11, 0b11, "ld1rd", Z_d, ZPR64, uimm6s8>;
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// LD1RQ loads (load quadword-vector and splat to scalable vector)
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defm LD1RQ_B_IMM : sve_mem_ldqr_si<0b00, "ld1rqb", Z_b, ZPR8>;
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defm LD1RQ_H_IMM : sve_mem_ldqr_si<0b01, "ld1rqh", Z_h, ZPR16>;
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defm LD1RQ_W_IMM : sve_mem_ldqr_si<0b10, "ld1rqw", Z_s, ZPR32>;
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defm LD1RQ_D_IMM : sve_mem_ldqr_si<0b11, "ld1rqd", Z_d, ZPR64>;
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defm LD1RQ_B : sve_mem_ldqr_ss<0b00, "ld1rqb", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LD1RQ_H : sve_mem_ldqr_ss<0b01, "ld1rqh", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LD1RQ_W : sve_mem_ldqr_ss<0b10, "ld1rqw", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LD1RQ_D : sve_mem_ldqr_ss<0b11, "ld1rqd", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// continuous load with reg+reg addressing.
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defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// non-faulting continuous load with reg+immediate
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defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
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defm LDNF1B_H_IMM : sve_mem_cldnf_si<0b0001, "ldnf1b", Z_h, ZPR16>;
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defm LDNF1B_S_IMM : sve_mem_cldnf_si<0b0010, "ldnf1b", Z_s, ZPR32>;
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defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
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defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
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defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;
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defm LDNF1H_S_IMM : sve_mem_cldnf_si<0b0110, "ldnf1h", Z_s, ZPR32>;
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defm LDNF1H_D_IMM : sve_mem_cldnf_si<0b0111, "ldnf1h", Z_d, ZPR64>;
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defm LDNF1SH_D_IMM : sve_mem_cldnf_si<0b1000, "ldnf1sh", Z_d, ZPR64>;
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defm LDNF1SH_S_IMM : sve_mem_cldnf_si<0b1001, "ldnf1sh", Z_s, ZPR32>;
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defm LDNF1W_IMM : sve_mem_cldnf_si<0b1010, "ldnf1w", Z_s, ZPR32>;
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defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
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defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
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defm LDNF1SB_S_IMM : sve_mem_cldnf_si<0b1101, "ldnf1sb", Z_s, ZPR32>;
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defm LDNF1SB_H_IMM : sve_mem_cldnf_si<0b1110, "ldnf1sb", Z_h, ZPR16>;
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defm LDNF1D_IMM : sve_mem_cldnf_si<0b1111, "ldnf1d", Z_d, ZPR64>;
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// First-faulting loads with reg+reg addressing.
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defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>;
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defm LDFF1B_H : sve_mem_cldff_ss<0b0001, "ldff1b", Z_h, ZPR16, GPR64shifted8>;
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defm LDFF1B_S : sve_mem_cldff_ss<0b0010, "ldff1b", Z_s, ZPR32, GPR64shifted8>;
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defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>;
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defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>;
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defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;
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defm LDFF1H_S : sve_mem_cldff_ss<0b0110, "ldff1h", Z_s, ZPR32, GPR64shifted16>;
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defm LDFF1H_D : sve_mem_cldff_ss<0b0111, "ldff1h", Z_d, ZPR64, GPR64shifted16>;
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defm LDFF1SH_D : sve_mem_cldff_ss<0b1000, "ldff1sh", Z_d, ZPR64, GPR64shifted16>;
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defm LDFF1SH_S : sve_mem_cldff_ss<0b1001, "ldff1sh", Z_s, ZPR32, GPR64shifted16>;
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defm LDFF1W : sve_mem_cldff_ss<0b1010, "ldff1w", Z_s, ZPR32, GPR64shifted32>;
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defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
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defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>;
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defm LDFF1SB_S : sve_mem_cldff_ss<0b1101, "ldff1sb", Z_s, ZPR32, GPR64shifted8>;
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defm LDFF1SB_H : sve_mem_cldff_ss<0b1110, "ldff1sb", Z_h, ZPR16, GPR64shifted8>;
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defm LDFF1D : sve_mem_cldff_ss<0b1111, "ldff1d", Z_d, ZPR64, GPR64shifted64>;
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// LD(2|3|4) structured loads with reg+immediate
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defm LD2B_IMM : sve_mem_eld_si<0b00, 0b01, ZZ_b, "ld2b", simm4s2>;
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defm LD3B_IMM : sve_mem_eld_si<0b00, 0b10, ZZZ_b, "ld3b", simm4s3>;
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defm LD4B_IMM : sve_mem_eld_si<0b00, 0b11, ZZZZ_b, "ld4b", simm4s4>;
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defm LD2H_IMM : sve_mem_eld_si<0b01, 0b01, ZZ_h, "ld2h", simm4s2>;
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defm LD3H_IMM : sve_mem_eld_si<0b01, 0b10, ZZZ_h, "ld3h", simm4s3>;
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defm LD4H_IMM : sve_mem_eld_si<0b01, 0b11, ZZZZ_h, "ld4h", simm4s4>;
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defm LD2W_IMM : sve_mem_eld_si<0b10, 0b01, ZZ_s, "ld2w", simm4s2>;
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defm LD3W_IMM : sve_mem_eld_si<0b10, 0b10, ZZZ_s, "ld3w", simm4s3>;
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defm LD4W_IMM : sve_mem_eld_si<0b10, 0b11, ZZZZ_s, "ld4w", simm4s4>;
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defm LD2D_IMM : sve_mem_eld_si<0b11, 0b01, ZZ_d, "ld2d", simm4s2>;
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defm LD3D_IMM : sve_mem_eld_si<0b11, 0b10, ZZZ_d, "ld3d", simm4s3>;
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defm LD4D_IMM : sve_mem_eld_si<0b11, 0b11, ZZZZ_d, "ld4d", simm4s4>;
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// LD(2|3|4) structured loads (register + register)
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def LD2B : sve_mem_eld_ss<0b00, 0b01, ZZ_b, "ld2b", GPR64NoXZRshifted8>;
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def LD3B : sve_mem_eld_ss<0b00, 0b10, ZZZ_b, "ld3b", GPR64NoXZRshifted8>;
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def LD4B : sve_mem_eld_ss<0b00, 0b11, ZZZZ_b, "ld4b", GPR64NoXZRshifted8>;
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def LD2H : sve_mem_eld_ss<0b01, 0b01, ZZ_h, "ld2h", GPR64NoXZRshifted16>;
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def LD3H : sve_mem_eld_ss<0b01, 0b10, ZZZ_h, "ld3h", GPR64NoXZRshifted16>;
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def LD4H : sve_mem_eld_ss<0b01, 0b11, ZZZZ_h, "ld4h", GPR64NoXZRshifted16>;
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def LD2W : sve_mem_eld_ss<0b10, 0b01, ZZ_s, "ld2w", GPR64NoXZRshifted32>;
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def LD3W : sve_mem_eld_ss<0b10, 0b10, ZZZ_s, "ld3w", GPR64NoXZRshifted32>;
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def LD4W : sve_mem_eld_ss<0b10, 0b11, ZZZZ_s, "ld4w", GPR64NoXZRshifted32>;
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def LD2D : sve_mem_eld_ss<0b11, 0b01, ZZ_d, "ld2d", GPR64NoXZRshifted64>;
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def LD3D : sve_mem_eld_ss<0b11, 0b10, ZZZ_d, "ld3d", GPR64NoXZRshifted64>;
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def LD4D : sve_mem_eld_ss<0b11, 0b11, ZZZZ_d, "ld4d", GPR64NoXZRshifted64>;
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// Gathers using unscaled 32-bit offsets, e.g.
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// ld1h z0.s, p0/z, [x0, z0.s, uxtw]
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defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLDFF1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLD1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLD1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1H_S : sve_mem_32b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLD1W : sve_mem_32b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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// Gathers using scaled 32-bit offsets, e.g.
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// ld1h z0.s, p0/z, [x0, z0.s, uxtw #1]
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defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLD1H_S : sve_mem_32b_gld_sv_32_scaled<0b0110, "ld1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLDFF1H_S : sve_mem_32b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm GLD1W : sve_mem_32b_gld_sv_32_scaled<0b1010, "ld1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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// Gathers using scaled 32-bit pointers with offset, e.g.
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// ld1h z0.s, p0/z, [z0.s, #16]
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defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>;
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defm GLDFF1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0001, "ldff1sb", imm0_31>;
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defm GLD1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0010, "ld1b", imm0_31>;
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defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>;
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defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2>;
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defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;
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defm GLD1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0110, "ld1h", uimm5s2>;
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defm GLDFF1H_S : sve_mem_32b_gld_vi_32_ptrs<0b0111, "ldff1h", uimm5s2>;
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defm GLD1W : sve_mem_32b_gld_vi_32_ptrs<0b1010, "ld1w", uimm5s4>;
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defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4>;
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// Gathers using scaled 64-bit pointers with offset, e.g.
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// ld1h z0.d, p0/z, [z0.d, #16]
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defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>;
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defm GLDFF1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0001, "ldff1sb", imm0_31>;
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defm GLD1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0010, "ld1b", imm0_31>;
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defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>;
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defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2>;
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defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;
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defm GLD1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0110, "ld1h", uimm5s2>;
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defm GLDFF1H_D : sve_mem_64b_gld_vi_64_ptrs<0b0111, "ldff1h", uimm5s2>;
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defm GLD1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1000, "ld1sw", uimm5s4>;
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defm GLDFF1SW_D : sve_mem_64b_gld_vi_64_ptrs<0b1001, "ldff1sw", uimm5s4>;
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defm GLD1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1010, "ld1w", uimm5s4>;
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defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4>;
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defm GLD1D : sve_mem_64b_gld_vi_64_ptrs<0b1110, "ld1d", uimm5s8>;
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defm GLDFF1D : sve_mem_64b_gld_vi_64_ptrs<0b1111, "ldff1d", uimm5s8>;
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// Gathers using unscaled 64-bit offsets, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d]
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defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
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defm GLDFF1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0001, "ldff1sb">;
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defm GLD1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0010, "ld1b">;
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defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
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defm GLD1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0100, "ld1sh">;
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defm GLDFF1SH_D : sve_mem_64b_gld_vs2_64_unscaled<0b0101, "ldff1sh">;
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defm GLD1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0110, "ld1h">;
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defm GLDFF1H_D : sve_mem_64b_gld_vs2_64_unscaled<0b0111, "ldff1h">;
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defm GLD1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1000, "ld1sw">;
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defm GLDFF1SW_D : sve_mem_64b_gld_vs2_64_unscaled<0b1001, "ldff1sw">;
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defm GLD1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1010, "ld1w">;
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defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w">;
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defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d">;
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defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d">;
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// Gathers using scaled 64-bit offsets, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
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defm GLD1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0100, "ld1sh", ZPR64ExtLSL16>;
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defm GLDFF1SH_D : sve_mem_64b_gld_sv2_64_scaled<0b0101, "ldff1sh", ZPR64ExtLSL16>;
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defm GLD1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0110, "ld1h", ZPR64ExtLSL16>;
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defm GLDFF1H_D : sve_mem_64b_gld_sv2_64_scaled<0b0111, "ldff1h", ZPR64ExtLSL16>;
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defm GLD1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1000, "ld1sw", ZPR64ExtLSL32>;
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defm GLDFF1SW_D : sve_mem_64b_gld_sv2_64_scaled<0b1001, "ldff1sw", ZPR64ExtLSL32>;
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defm GLD1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1010, "ld1w", ZPR64ExtLSL32>;
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defm GLDFF1W_D : sve_mem_64b_gld_sv2_64_scaled<0b1011, "ldff1w", ZPR64ExtLSL32>;
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defm GLD1D : sve_mem_64b_gld_sv2_64_scaled<0b1110, "ld1d", ZPR64ExtLSL64>;
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defm GLDFF1D : sve_mem_64b_gld_sv2_64_scaled<0b1111, "ldff1d", ZPR64ExtLSL64>;
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// Gathers using unscaled 32-bit offsets unpacked in 64-bits elements, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, uxtw]
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defm GLD1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLDFF1SB_D : sve_mem_64b_gld_vs_32_unscaled<0b0001, "ldff1sb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLD1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0010, "ld1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLDFF1B_D : sve_mem_64b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm GLD1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0100, "ld1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1SH_D : sve_mem_64b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0110, "ld1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1H_D : sve_mem_64b_gld_vs_32_unscaled<0b0111, "ldff1h", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1000, "ld1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1SW_D : sve_mem_64b_gld_vs_32_unscaled<0b1001, "ldff1sw", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1010, "ld1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1W_D : sve_mem_64b_gld_vs_32_unscaled<0b1011, "ldff1w", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLD1D : sve_mem_64b_gld_vs_32_unscaled<0b1110, "ld1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm GLDFF1D : sve_mem_64b_gld_vs_32_unscaled<0b1111, "ldff1d", ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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// Gathers using scaled 32-bit offsets unpacked in 64-bits elements, e.g.
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// ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
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defm GLD1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0100, "ld1sh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLDFF1SH_D : sve_mem_64b_gld_sv_32_scaled<0b0101, "ldff1sh",ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLD1H_D : sve_mem_64b_gld_sv_32_scaled<0b0110, "ld1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLDFF1H_D : sve_mem_64b_gld_sv_32_scaled<0b0111, "ldff1h", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm GLD1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1000, "ld1sw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLDFF1SW_D : sve_mem_64b_gld_sv_32_scaled<0b1001, "ldff1sw",ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLD1W_D : sve_mem_64b_gld_sv_32_scaled<0b1010, "ld1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLDFF1W_D : sve_mem_64b_gld_sv_32_scaled<0b1011, "ldff1w", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm GLD1D : sve_mem_64b_gld_sv_32_scaled<0b1110, "ld1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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defm GLDFF1D : sve_mem_64b_gld_sv_32_scaled<0b1111, "ldff1d", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Non-temporal contiguous loads (register + immediate)
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defm LDNT1B_ZRI : sve_mem_cldnt_si<0b00, "ldnt1b", Z_b, ZPR8>;
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defm LDNT1H_ZRI : sve_mem_cldnt_si<0b01, "ldnt1h", Z_h, ZPR16>;
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defm LDNT1W_ZRI : sve_mem_cldnt_si<0b10, "ldnt1w", Z_s, ZPR32>;
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defm LDNT1D_ZRI : sve_mem_cldnt_si<0b11, "ldnt1d", Z_d, ZPR64>;
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// Non-temporal contiguous loads (register + register)
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defm LDNT1B_ZRR : sve_mem_cldnt_ss<0b00, "ldnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm LDNT1H_ZRR : sve_mem_cldnt_ss<0b01, "ldnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm LDNT1W_ZRR : sve_mem_cldnt_ss<0b10, "ldnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm LDNT1D_ZRR : sve_mem_cldnt_ss<0b11, "ldnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// contiguous store with immediates
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defm ST1B_IMM : sve_mem_cst_si<0b00, 0b00, "st1b", Z_b, ZPR8>;
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defm ST1B_H_IMM : sve_mem_cst_si<0b00, 0b01, "st1b", Z_h, ZPR16>;
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defm ST1B_S_IMM : sve_mem_cst_si<0b00, 0b10, "st1b", Z_s, ZPR32>;
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defm ST1B_D_IMM : sve_mem_cst_si<0b00, 0b11, "st1b", Z_d, ZPR64>;
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defm ST1H_IMM : sve_mem_cst_si<0b01, 0b01, "st1h", Z_h, ZPR16>;
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defm ST1H_S_IMM : sve_mem_cst_si<0b01, 0b10, "st1h", Z_s, ZPR32>;
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defm ST1H_D_IMM : sve_mem_cst_si<0b01, 0b11, "st1h", Z_d, ZPR64>;
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defm ST1W_IMM : sve_mem_cst_si<0b10, 0b10, "st1w", Z_s, ZPR32>;
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defm ST1W_D_IMM : sve_mem_cst_si<0b10, 0b11, "st1w", Z_d, ZPR64>;
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defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>;
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// contiguous store with reg+reg addressing.
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defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>;
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defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>;
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defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
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defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>;
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defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>;
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defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
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defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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// Scatters using unscaled 32-bit offsets, e.g.
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// st1h z0.s, p0, [x0, z0.s, uxtw]
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// and unpacked:
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// st1h z0.d, p0, [x0, z0.d, uxtw]
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defm SST1B_D : sve_mem_sst_sv_32_unscaled<0b000, "st1b", Z_d, ZPR64, ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm SST1B_S : sve_mem_sst_sv_32_unscaled<0b001, "st1b", Z_s, ZPR32, ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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defm SST1H_D : sve_mem_sst_sv_32_unscaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm SST1H_S : sve_mem_sst_sv_32_unscaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm SST1W_D : sve_mem_sst_sv_32_unscaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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defm SST1W : sve_mem_sst_sv_32_unscaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW8, ZPR32ExtUXTW8>;
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defm SST1D : sve_mem_sst_sv_32_unscaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW8, ZPR64ExtUXTW8>;
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// Scatters using scaled 32-bit offsets, e.g.
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// st1h z0.s, p0, [x0, z0.s, uxtw #1]
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// and unpacked:
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// st1h z0.d, p0, [x0, z0.d, uxtw #1]
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defm SST1H_D : sve_mem_sst_sv_32_scaled<0b010, "st1h", Z_d, ZPR64, ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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defm SST1H_S : sve_mem_sst_sv_32_scaled<0b011, "st1h", Z_s, ZPR32, ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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defm SST1W_D : sve_mem_sst_sv_32_scaled<0b100, "st1w", Z_d, ZPR64, ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm SST1W : sve_mem_sst_sv_32_scaled<0b101, "st1w", Z_s, ZPR32, ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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defm SST1D : sve_mem_sst_sv_32_scaled<0b110, "st1d", Z_d, ZPR64, ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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// Scatters using 32/64-bit pointers with offset, e.g.
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// st1h z0.s, p0, [z0.s, #16]
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// st1h z0.d, p0, [z0.d, #16]
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defm SST1B_D : sve_mem_sst_vi_ptrs<0b000, "st1b", Z_d, ZPR64, imm0_31>;
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defm SST1B_S : sve_mem_sst_vi_ptrs<0b001, "st1b", Z_s, ZPR32, imm0_31>;
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defm SST1H_D : sve_mem_sst_vi_ptrs<0b010, "st1h", Z_d, ZPR64, uimm5s2>;
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defm SST1H_S : sve_mem_sst_vi_ptrs<0b011, "st1h", Z_s, ZPR32, uimm5s2>;
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defm SST1W_D : sve_mem_sst_vi_ptrs<0b100, "st1w", Z_d, ZPR64, uimm5s4>;
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defm SST1W : sve_mem_sst_vi_ptrs<0b101, "st1w", Z_s, ZPR32, uimm5s4>;
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defm SST1D : sve_mem_sst_vi_ptrs<0b110, "st1d", Z_d, ZPR64, uimm5s8>;
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// Scatters using unscaled 64-bit offsets, e.g.
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// st1h z0.d, p0, [x0, z0.d]
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defm SST1B_D : sve_mem_sst_sv_64_unscaled<0b00, "st1b">;
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defm SST1H_D : sve_mem_sst_sv_64_unscaled<0b01, "st1h">;
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defm SST1W_D : sve_mem_sst_sv_64_unscaled<0b10, "st1w">;
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defm SST1D : sve_mem_sst_sv_64_unscaled<0b11, "st1d">;
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// Scatters using scaled 64-bit offsets, e.g.
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// st1h z0.d, p0, [x0, z0.d, lsl #1]
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defm SST1H_D_SCALED : sve_mem_sst_sv_64_scaled<0b01, "st1h", ZPR64ExtLSL16>;
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defm SST1W_D_SCALED : sve_mem_sst_sv_64_scaled<0b10, "st1w", ZPR64ExtLSL32>;
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defm SST1D_SCALED : sve_mem_sst_sv_64_scaled<0b11, "st1d", ZPR64ExtLSL64>;
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// ST(2|3|4) structured stores (register + immediate)
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defm ST2B_IMM : sve_mem_est_si<0b00, 0b01, ZZ_b, "st2b", simm4s2>;
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defm ST3B_IMM : sve_mem_est_si<0b00, 0b10, ZZZ_b, "st3b", simm4s3>;
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defm ST4B_IMM : sve_mem_est_si<0b00, 0b11, ZZZZ_b, "st4b", simm4s4>;
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defm ST2H_IMM : sve_mem_est_si<0b01, 0b01, ZZ_h, "st2h", simm4s2>;
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defm ST3H_IMM : sve_mem_est_si<0b01, 0b10, ZZZ_h, "st3h", simm4s3>;
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defm ST4H_IMM : sve_mem_est_si<0b01, 0b11, ZZZZ_h, "st4h", simm4s4>;
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defm ST2W_IMM : sve_mem_est_si<0b10, 0b01, ZZ_s, "st2w", simm4s2>;
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defm ST3W_IMM : sve_mem_est_si<0b10, 0b10, ZZZ_s, "st3w", simm4s3>;
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defm ST4W_IMM : sve_mem_est_si<0b10, 0b11, ZZZZ_s, "st4w", simm4s4>;
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defm ST2D_IMM : sve_mem_est_si<0b11, 0b01, ZZ_d, "st2d", simm4s2>;
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defm ST3D_IMM : sve_mem_est_si<0b11, 0b10, ZZZ_d, "st3d", simm4s3>;
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defm ST4D_IMM : sve_mem_est_si<0b11, 0b11, ZZZZ_d, "st4d", simm4s4>;
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// ST(2|3|4) structured stores (register + register)
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def ST2B : sve_mem_est_ss<0b00, 0b01, ZZ_b, "st2b", GPR64NoXZRshifted8>;
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def ST3B : sve_mem_est_ss<0b00, 0b10, ZZZ_b, "st3b", GPR64NoXZRshifted8>;
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def ST4B : sve_mem_est_ss<0b00, 0b11, ZZZZ_b, "st4b", GPR64NoXZRshifted8>;
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def ST2H : sve_mem_est_ss<0b01, 0b01, ZZ_h, "st2h", GPR64NoXZRshifted16>;
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def ST3H : sve_mem_est_ss<0b01, 0b10, ZZZ_h, "st3h", GPR64NoXZRshifted16>;
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def ST4H : sve_mem_est_ss<0b01, 0b11, ZZZZ_h, "st4h", GPR64NoXZRshifted16>;
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def ST2W : sve_mem_est_ss<0b10, 0b01, ZZ_s, "st2w", GPR64NoXZRshifted32>;
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def ST3W : sve_mem_est_ss<0b10, 0b10, ZZZ_s, "st3w", GPR64NoXZRshifted32>;
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def ST4W : sve_mem_est_ss<0b10, 0b11, ZZZZ_s, "st4w", GPR64NoXZRshifted32>;
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def ST2D : sve_mem_est_ss<0b11, 0b01, ZZ_d, "st2d", GPR64NoXZRshifted64>;
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def ST3D : sve_mem_est_ss<0b11, 0b10, ZZZ_d, "st3d", GPR64NoXZRshifted64>;
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def ST4D : sve_mem_est_ss<0b11, 0b11, ZZZZ_d, "st4d", GPR64NoXZRshifted64>;
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// Non-temporal contiguous stores (register + immediate)
|
|
defm STNT1B_ZRI : sve_mem_cstnt_si<0b00, "stnt1b", Z_b, ZPR8>;
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defm STNT1H_ZRI : sve_mem_cstnt_si<0b01, "stnt1h", Z_h, ZPR16>;
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defm STNT1W_ZRI : sve_mem_cstnt_si<0b10, "stnt1w", Z_s, ZPR32>;
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defm STNT1D_ZRI : sve_mem_cstnt_si<0b11, "stnt1d", Z_d, ZPR64>;
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// Non-temporal contiguous stores (register + register)
|
|
defm STNT1B_ZRR : sve_mem_cstnt_ss<0b00, "stnt1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
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defm STNT1H_ZRR : sve_mem_cstnt_ss<0b01, "stnt1h", Z_h, ZPR16, GPR64NoXZRshifted16>;
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defm STNT1W_ZRR : sve_mem_cstnt_ss<0b10, "stnt1w", Z_s, ZPR32, GPR64NoXZRshifted32>;
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defm STNT1D_ZRR : sve_mem_cstnt_ss<0b11, "stnt1d", Z_d, ZPR64, GPR64NoXZRshifted64>;
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|
|
// Fill/Spill
|
|
defm LDR_ZXI : sve_mem_z_fill<"ldr">;
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defm LDR_PXI : sve_mem_p_fill<"ldr">;
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|
defm STR_ZXI : sve_mem_z_spill<"str">;
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|
defm STR_PXI : sve_mem_p_spill<"str">;
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|
|
// Contiguous prefetch (register + immediate)
|
|
defm PRFB_PRI : sve_mem_prfm_si<0b00, "prfb">;
|
|
defm PRFH_PRI : sve_mem_prfm_si<0b01, "prfh">;
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|
defm PRFW_PRI : sve_mem_prfm_si<0b10, "prfw">;
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|
defm PRFD_PRI : sve_mem_prfm_si<0b11, "prfd">;
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|
|
|
// Contiguous prefetch (register + register)
|
|
def PRFB_PRR : sve_mem_prfm_ss<0b001, "prfb", GPR64NoXZRshifted8>;
|
|
def PRFH_PRR : sve_mem_prfm_ss<0b011, "prfh", GPR64NoXZRshifted16>;
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|
def PRFS_PRR : sve_mem_prfm_ss<0b101, "prfw", GPR64NoXZRshifted32>;
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|
def PRFD_PRR : sve_mem_prfm_ss<0b111, "prfd", GPR64NoXZRshifted64>;
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|
|
|
// Gather prefetch using scaled 32-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.s, uxtw #1]
|
|
defm PRFB_S : sve_mem_32b_prfm_sv_scaled<0b00, "prfb", ZPR32ExtSXTW8Only, ZPR32ExtUXTW8Only>;
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|
defm PRFH_S : sve_mem_32b_prfm_sv_scaled<0b01, "prfh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;
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|
defm PRFW_S : sve_mem_32b_prfm_sv_scaled<0b10, "prfw", ZPR32ExtSXTW32, ZPR32ExtUXTW32>;
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|
defm PRFD_S : sve_mem_32b_prfm_sv_scaled<0b11, "prfd", ZPR32ExtSXTW64, ZPR32ExtUXTW64>;
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|
|
// Gather prefetch using unpacked, scaled 32-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.d, uxtw #1]
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|
defm PRFB_D : sve_mem_64b_prfm_sv_ext_scaled<0b00, "prfb", ZPR64ExtSXTW8Only, ZPR64ExtUXTW8Only>;
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defm PRFH_D : sve_mem_64b_prfm_sv_ext_scaled<0b01, "prfh", ZPR64ExtSXTW16, ZPR64ExtUXTW16>;
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|
defm PRFW_D : sve_mem_64b_prfm_sv_ext_scaled<0b10, "prfw", ZPR64ExtSXTW32, ZPR64ExtUXTW32>;
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defm PRFD_D : sve_mem_64b_prfm_sv_ext_scaled<0b11, "prfd", ZPR64ExtSXTW64, ZPR64ExtUXTW64>;
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|
|
// Gather prefetch using scaled 64-bit offsets, e.g.
|
|
// prfh pldl1keep, p0, [x0, z0.d, lsl #1]
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defm PRFB_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b00, "prfb", ZPR64ExtLSL8>;
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defm PRFH_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b01, "prfh", ZPR64ExtLSL16>;
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defm PRFW_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b10, "prfw", ZPR64ExtLSL32>;
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defm PRFD_D_SCALED : sve_mem_64b_prfm_sv_lsl_scaled<0b11, "prfd", ZPR64ExtLSL64>;
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|
|
// Gather prefetch using 32/64-bit pointers with offset, e.g.
|
|
// prfh pldl1keep, p0, [z0.s, #16]
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// prfh pldl1keep, p0, [z0.d, #16]
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|
defm PRFB_S_PZI : sve_mem_32b_prfm_vi<0b00, "prfb", imm0_31>;
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defm PRFH_S_PZI : sve_mem_32b_prfm_vi<0b01, "prfh", uimm5s2>;
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defm PRFW_S_PZI : sve_mem_32b_prfm_vi<0b10, "prfw", uimm5s4>;
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defm PRFD_S_PZI : sve_mem_32b_prfm_vi<0b11, "prfd", uimm5s8>;
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|
defm PRFB_D_PZI : sve_mem_64b_prfm_vi<0b00, "prfb", imm0_31>;
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defm PRFH_D_PZI : sve_mem_64b_prfm_vi<0b01, "prfh", uimm5s2>;
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|
defm PRFW_D_PZI : sve_mem_64b_prfm_vi<0b10, "prfw", uimm5s4>;
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|
defm PRFD_D_PZI : sve_mem_64b_prfm_vi<0b11, "prfd", uimm5s8>;
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|
defm ZIP1_ZZZ : sve_int_perm_bin_perm_zz<0b000, "zip1">;
|
|
defm ZIP2_ZZZ : sve_int_perm_bin_perm_zz<0b001, "zip2">;
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|
defm ZIP1_PPP : sve_int_perm_bin_perm_pp<0b000, "zip1">;
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defm ZIP2_PPP : sve_int_perm_bin_perm_pp<0b001, "zip2">;
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|
def RDVLI_XI : sve_int_read_vl_a<0b0, 0b11111, "rdvl">;
|
|
def ADDVL_XXI : sve_int_arith_vl<0b0, "addvl">;
|
|
def ADDPL_XXI : sve_int_arith_vl<0b1, "addpl">;
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|
|
|
defm INCB_XPiI : sve_int_pred_pattern_a<0b000, "incb">;
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defm DECB_XPiI : sve_int_pred_pattern_a<0b001, "decb">;
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|
defm INCH_XPiI : sve_int_pred_pattern_a<0b010, "inch">;
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|
defm DECH_XPiI : sve_int_pred_pattern_a<0b011, "dech">;
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|
defm INCW_XPiI : sve_int_pred_pattern_a<0b100, "incw">;
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|
defm DECW_XPiI : sve_int_pred_pattern_a<0b101, "decw">;
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|
defm INCD_XPiI : sve_int_pred_pattern_a<0b110, "incd">;
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|
defm DECD_XPiI : sve_int_pred_pattern_a<0b111, "decd">;
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|
|
|
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">;
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|
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">;
|
|
defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">;
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|
defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt">;
|
|
defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq">;
|
|
defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne">;
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|
|
|
defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq">;
|
|
defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne">;
|
|
defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge">;
|
|
defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt">;
|
|
defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt">;
|
|
defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple">;
|
|
defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs">;
|
|
defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi">;
|
|
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
|
|
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
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|
|
|
defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge">;
|
|
defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt">;
|
|
defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt">;
|
|
defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple">;
|
|
defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq">;
|
|
defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne">;
|
|
defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs">;
|
|
defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi">;
|
|
defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">;
|
|
defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">;
|
|
|
|
defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge">;
|
|
defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt">;
|
|
defm FCMEQ_PPzZZ : sve_fp_3op_p_pd<0b010, "fcmeq">;
|
|
defm FCMNE_PPzZZ : sve_fp_3op_p_pd<0b011, "fcmne">;
|
|
defm FCMUO_PPzZZ : sve_fp_3op_p_pd<0b100, "fcmuo">;
|
|
defm FACGE_PPzZZ : sve_fp_3op_p_pd<0b101, "facge">;
|
|
defm FACGT_PPzZZ : sve_fp_3op_p_pd<0b111, "facgt">;
|
|
|
|
defm FCMGE_PPzZ0 : sve_fp_2op_p_pd<0b000, "fcmge">;
|
|
defm FCMGT_PPzZ0 : sve_fp_2op_p_pd<0b001, "fcmgt">;
|
|
defm FCMLT_PPzZ0 : sve_fp_2op_p_pd<0b010, "fcmlt">;
|
|
defm FCMLE_PPzZ0 : sve_fp_2op_p_pd<0b011, "fcmle">;
|
|
defm FCMEQ_PPzZ0 : sve_fp_2op_p_pd<0b100, "fcmeq">;
|
|
defm FCMNE_PPzZ0 : sve_fp_2op_p_pd<0b110, "fcmne">;
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|
|
|
defm SQINCB_XPiWdI : sve_int_pred_pattern_b_s32<0b00000, "sqincb">;
|
|
defm UQINCB_WPiI : sve_int_pred_pattern_b_u32<0b00001, "uqincb">;
|
|
defm SQDECB_XPiWdI : sve_int_pred_pattern_b_s32<0b00010, "sqdecb">;
|
|
defm UQDECB_WPiI : sve_int_pred_pattern_b_u32<0b00011, "uqdecb">;
|
|
defm SQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00100, "sqincb">;
|
|
defm UQINCB_XPiI : sve_int_pred_pattern_b_x64<0b00101, "uqincb">;
|
|
defm SQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00110, "sqdecb">;
|
|
defm UQDECB_XPiI : sve_int_pred_pattern_b_x64<0b00111, "uqdecb">;
|
|
|
|
defm SQINCH_XPiWdI : sve_int_pred_pattern_b_s32<0b01000, "sqinch">;
|
|
defm UQINCH_WPiI : sve_int_pred_pattern_b_u32<0b01001, "uqinch">;
|
|
defm SQDECH_XPiWdI : sve_int_pred_pattern_b_s32<0b01010, "sqdech">;
|
|
defm UQDECH_WPiI : sve_int_pred_pattern_b_u32<0b01011, "uqdech">;
|
|
defm SQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01100, "sqinch">;
|
|
defm UQINCH_XPiI : sve_int_pred_pattern_b_x64<0b01101, "uqinch">;
|
|
defm SQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01110, "sqdech">;
|
|
defm UQDECH_XPiI : sve_int_pred_pattern_b_x64<0b01111, "uqdech">;
|
|
|
|
defm SQINCW_XPiWdI : sve_int_pred_pattern_b_s32<0b10000, "sqincw">;
|
|
defm UQINCW_WPiI : sve_int_pred_pattern_b_u32<0b10001, "uqincw">;
|
|
defm SQDECW_XPiWdI : sve_int_pred_pattern_b_s32<0b10010, "sqdecw">;
|
|
defm UQDECW_WPiI : sve_int_pred_pattern_b_u32<0b10011, "uqdecw">;
|
|
defm SQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10100, "sqincw">;
|
|
defm UQINCW_XPiI : sve_int_pred_pattern_b_x64<0b10101, "uqincw">;
|
|
defm SQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10110, "sqdecw">;
|
|
defm UQDECW_XPiI : sve_int_pred_pattern_b_x64<0b10111, "uqdecw">;
|
|
|
|
defm SQINCD_XPiWdI : sve_int_pred_pattern_b_s32<0b11000, "sqincd">;
|
|
defm UQINCD_WPiI : sve_int_pred_pattern_b_u32<0b11001, "uqincd">;
|
|
defm SQDECD_XPiWdI : sve_int_pred_pattern_b_s32<0b11010, "sqdecd">;
|
|
defm UQDECD_WPiI : sve_int_pred_pattern_b_u32<0b11011, "uqdecd">;
|
|
defm SQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11100, "sqincd">;
|
|
defm UQINCD_XPiI : sve_int_pred_pattern_b_x64<0b11101, "uqincd">;
|
|
defm SQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
|
|
defm UQDECD_XPiI : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
|
|
|
|
defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>;
|
|
defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>;
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defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>;
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defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>;
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defm INCH_ZPiI : sve_int_countvlv<0b01100, "inch", ZPR16>;
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defm DECH_ZPiI : sve_int_countvlv<0b01101, "dech", ZPR16>;
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defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>;
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defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>;
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defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>;
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defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>;
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defm INCW_ZPiI : sve_int_countvlv<0b10100, "incw", ZPR32>;
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defm DECW_ZPiI : sve_int_countvlv<0b10101, "decw", ZPR32>;
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defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>;
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defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>;
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defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>;
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defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>;
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defm INCD_ZPiI : sve_int_countvlv<0b11100, "incd", ZPR64>;
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defm DECD_ZPiI : sve_int_countvlv<0b11101, "decd", ZPR64>;
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defm SQINCP_XPWd : sve_int_count_r_s32<0b00000, "sqincp">;
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defm SQINCP_XP : sve_int_count_r_x64<0b00010, "sqincp">;
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defm UQINCP_WP : sve_int_count_r_u32<0b00100, "uqincp">;
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defm UQINCP_XP : sve_int_count_r_x64<0b00110, "uqincp">;
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defm SQDECP_XPWd : sve_int_count_r_s32<0b01000, "sqdecp">;
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defm SQDECP_XP : sve_int_count_r_x64<0b01010, "sqdecp">;
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defm UQDECP_WP : sve_int_count_r_u32<0b01100, "uqdecp">;
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defm UQDECP_XP : sve_int_count_r_x64<0b01110, "uqdecp">;
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defm INCP_XP : sve_int_count_r_x64<0b10000, "incp">;
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defm DECP_XP : sve_int_count_r_x64<0b10100, "decp">;
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defm SQINCP_ZP : sve_int_count_v<0b00000, "sqincp">;
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defm UQINCP_ZP : sve_int_count_v<0b00100, "uqincp">;
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defm SQDECP_ZP : sve_int_count_v<0b01000, "sqdecp">;
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defm UQDECP_ZP : sve_int_count_v<0b01100, "uqdecp">;
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defm INCP_ZP : sve_int_count_v<0b10000, "incp">;
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defm DECP_ZP : sve_int_count_v<0b10100, "decp">;
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defm INDEX_RR : sve_int_index_rr<"index">;
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defm INDEX_IR : sve_int_index_ir<"index">;
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defm INDEX_RI : sve_int_index_ri<"index">;
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defm INDEX_II : sve_int_index_ii<"index">;
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defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">;
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defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
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defm LSR_ZPmZ : sve_int_bin_pred_shift_1<0b001, "lsr">;
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defm LSL_ZPmZ : sve_int_bin_pred_shift_1<0b011, "lsl">;
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// InstAliases
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def : InstAlias<"mov $Zd, $Zn",
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(ORR_ZZZ ZPR64:$Zd, ZPR64:$Zn, ZPR64:$Zn), 1>;
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def : InstAlias<"mov $Pd, $Pg/m, $Pn",
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(SEL_PPPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pd), 1>;
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def : InstAlias<"mov $Pd, $Pn",
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(ORR_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
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def : InstAlias<"mov $Pd, $Pg/z, $Pn",
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(AND_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
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def : InstAlias<"movs $Pd, $Pn",
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(ORRS_PPzPP PPR8:$Pd, PPR8:$Pn, PPR8:$Pn, PPR8:$Pn), 1>;
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def : InstAlias<"movs $Pd, $Pg/z, $Pn",
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(ANDS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPR8:$Pn), 1>;
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def : InstAlias<"not $Pd, $Pg/z, $Pn",
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(EOR_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
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def : InstAlias<"nots $Pd, $Pg/z, $Pn",
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(EORS_PPzPP PPR8:$Pd, PPRAny:$Pg, PPR8:$Pn, PPRAny:$Pg), 1>;
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def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
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(CMPGE_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
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def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
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(CMPGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
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(CMPGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"cmple $Zd, $Pg/z, $Zm, $Zn",
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(CMPGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
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(CMPHI_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
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def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
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(CMPHI_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
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(CMPHI_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"cmplo $Zd, $Pg/z, $Zm, $Zn",
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(CMPHI_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
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(CMPHS_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
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def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
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(CMPHS_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
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(CMPHS_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"cmpls $Zd, $Pg/z, $Zm, $Zn",
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(CMPHS_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
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(CMPGT_PPzZZ_B PPR8:$Zd, PPR3bAny:$Pg, ZPR8:$Zn, ZPR8:$Zm), 0>;
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def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
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(CMPGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
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(CMPGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"cmplt $Zd, $Pg/z, $Zm, $Zn",
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(CMPGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
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(FACGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
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(FACGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"facle $Zd, $Pg/z, $Zm, $Zn",
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(FACGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
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(FACGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
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(FACGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"faclt $Zd, $Pg/z, $Zm, $Zn",
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(FACGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
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(FCMGE_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
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(FCMGE_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"fcmle $Zd, $Pg/z, $Zm, $Zn",
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(FCMGE_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
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(FCMGT_PPzZZ_H PPR16:$Zd, PPR3bAny:$Pg, ZPR16:$Zn, ZPR16:$Zm), 0>;
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def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
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(FCMGT_PPzZZ_S PPR32:$Zd, PPR3bAny:$Pg, ZPR32:$Zn, ZPR32:$Zm), 0>;
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def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
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(FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
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}
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