llvm-project/llvm/test/MC/Mips/mips64r6
Simon Atanasyan e80c3ce9cc [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions
The `MipsAsmParser::loadImmediate` can load immediates of various sizes
into a register. Idea of this change is to use `loadImmediate` in the
`MipsAsmParser::expandMemInst` method to load offset into a register and
then call required load/store instruction.

The patch removes separate `expandLoadInst` and `expandStoreInst`
methods and does everything in the `expandMemInst` method to escape code
duplication.

Differential Revision: https://reviews.llvm.org/D47316

llvm-svn: 333774
2018-06-01 16:37:53 +00:00
..
invalid-mips1-wrong-error.s [mips] Correct the predicates of the load/store (double)word for coprocessor 3. 2018-04-12 14:41:38 +00:00
invalid-mips1.s
invalid-mips2.s
invalid-mips3-wrong-error.s [AArch64][SVE] Re-submit patch series for ZIP1/ZIP2 2017-12-20 11:02:42 +00:00
invalid-mips3.s
invalid-mips4-wrong-error.s
invalid-mips4.s
invalid-mips5-wrong-error.s
invalid-mips5.s
invalid-mips32-wrong-error.s
invalid-mips64.s
invalid.s [mips] Support 64-bit offsets for lb/sb/ld/sd/lld ... instructions 2018-06-01 16:37:53 +00:00
relocations.s [mips][microMIPS] add lapc instruction 2017-09-11 18:34:04 +00:00
valid.s [mips] Fix the predicates of round, ceiling, floor and trunc. 2018-05-14 16:26:50 +00:00