forked from OSchip/llvm-project
62 lines
1.9 KiB
LLVM
62 lines
1.9 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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; Test that we generate the correct offsets for loads in the prolog
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; after removing dependences on a post-increment instructions of the
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; base register.
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; CHECK: memh([[REG0:(r[0-9]+)]]+#0)
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; CHECK: memh([[REG0]]+#2)
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; CHECK: loop0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.sath(i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.asrh(i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.A2.addsat(i32, i32) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32, i32) #1
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define void @f0(i32 %a0) #0 align 2 {
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b0:
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br label %b1
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b1: ; preds = %b0
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br label %b2
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b2: ; preds = %b2, %b1
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%v0 = phi i16* [ undef, %b1 ], [ %v14, %b2 ]
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%v1 = phi i32 [ 0, %b1 ], [ %v12, %b2 ]
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%v2 = load i16, i16* %v0, align 2
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%v3 = sext i16 %v2 to i32
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%v4 = call i32 @llvm.hexagon.M2.mpy.sat.ll.s1(i32 undef, i32 %v3)
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%v5 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v4, i32 undef)
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%v6 = call i32 @llvm.hexagon.A2.addsat(i32 %v5, i32 32768)
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%v7 = call i32 @llvm.hexagon.A2.asrh(i32 %v6)
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%v8 = call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v7, i32 undef)
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%v9 = call i32 @llvm.hexagon.A2.sath(i32 %v8)
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%v10 = trunc i32 %v9 to i16
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store i16 %v10, i16* null, align 2
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%v11 = trunc i32 %v7 to i16
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store i16 %v11, i16* %v0, align 2
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%v12 = add nsw i32 %v1, 1
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%v13 = icmp slt i32 %v12, %a0
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%v14 = getelementptr i16, i16* %v0, i32 1
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br i1 %v13, label %b2, label %b3
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b3: ; preds = %b2
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unreachable
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b4: ; No predecessors!
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unreachable
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" }
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attributes #1 = { nounwind readnone }
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