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AsmParser
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RISCV: add a few deprecated aliases for CSRs
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2021-05-21 13:52:58 -07:00 |
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Disassembler
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[RISCV] Fix shared libs build
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2021-02-09 06:14:25 -06:00 |
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MCTargetDesc
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Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"
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2021-05-29 15:11:37 +01:00 |
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TargetInfo
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CMakeLists.txt
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCV.h
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCV.td
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[RISCV][NFC] Fix formatting
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2021-04-09 14:41:09 +08:00 |
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RISCVAsmPrinter.cpp
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[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
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2021-05-10 09:33:23 +08:00 |
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCVFrameLowering.cpp
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[RISCV] Reserve an emergency spill slot for any RVV spills
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2021-06-03 10:44:34 +01:00 |
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RISCVFrameLowering.h
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[RISCV] Fix offset computation for RVV
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2021-03-29 17:03:49 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
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2021-06-04 09:17:46 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Optimize SEW=64 shifts by splat on RV32.
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2021-05-26 10:23:32 -07:00 |
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RISCVISelLowering.cpp
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[RISCV] Expand unaligned fixed-length vector memory accesses
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2021-06-02 09:27:44 +01:00 |
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RISCVISelLowering.h
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[RISCV] Support vector types in combination with fastcc
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2021-06-01 10:31:18 +01:00 |
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RISCVInsertVSETVLI.cpp
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[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.
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2021-06-04 09:17:46 -07:00 |
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RISCVInstrFormats.td
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[RISCV] Cleanup instruction formats used for B extension ternary operations.
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2021-05-06 08:59:05 -07:00 |
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[RISCV] Reserve an emergency spill slot for any RVV spills
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2021-06-03 10:44:34 +01:00 |
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RISCVInstrInfo.h
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[RISCV] Reserve an emergency spill slot for any RVV spills
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2021-06-03 10:44:34 +01:00 |
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RISCVInstrInfo.td
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[RISCV] Replace AddiPair ComplexPattern with a PatLeaf. NFC
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2021-05-16 12:17:52 -07:00 |
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RISCVInstrInfoA.td
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[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
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2021-04-09 09:37:04 +08:00 |
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RISCVInstrInfoB.td
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[RISCV] Optimize xor/or with immediate in the zbs extension
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2021-05-25 14:14:09 +08:00 |
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RISCVInstrInfoC.td
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[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
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2021-03-19 20:39:49 -07:00 |
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RISCVInstrInfoD.td
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[RISCV] Cleanup instruction formats used for B extension ternary operations.
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2021-05-06 08:59:05 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Cleanup instruction formats used for B extension ternary operations.
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2021-05-06 08:59:05 -07:00 |
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RISCVInstrInfoM.td
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[RISCV] Add custom type legalization to form MULHSU when possible.
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2021-04-01 10:15:55 -07:00 |
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RISCVInstrInfoV.td
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[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
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2021-04-21 14:50:29 -07:00 |
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RISCVInstrInfoVPseudos.td
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[RISCV] Replace (XLenVT (VLOp GPR:$vl)) with VLOpFrag
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2021-06-05 12:49:31 +08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Minor vector instruction tablegen cleanup. NFC
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2021-05-06 11:23:59 -07:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Add octuple to LMULInfo tablegen class, remove octuple_from_str. NFCI
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2021-05-28 11:53:05 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Cleanup instruction formats used for B extension ternary operations.
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2021-05-06 08:59:05 -07:00 |
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RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
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2021-06-01 13:23:48 -07:00 |
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
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[RISCV] Move instruction information into the RISCVII namespace (NFC)
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2021-05-11 16:32:42 -05:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Don't emit save-restore call if function is a interrupt handler
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2021-04-16 12:54:47 +08:00 |
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RISCVMergeBaseOffset.cpp
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RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
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[RISCV] Reserve an emergency spill slot for any RVV spills
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2021-06-03 10:44:34 +01:00 |
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RISCVRegisterInfo.h
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[RISCV] Improve register allocation around vector masks
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2021-02-20 14:47:51 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Introduce floating point control and state registers
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2021-04-21 12:55:30 +07:00 |
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RISCVSchedRocket.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedSiFive7.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVSchedule.td
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[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
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2021-03-31 15:06:14 -07:00 |
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RISCVScheduleB.td
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[RISCV] Move scheduling resources for B into a separate file (NFC)
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2021-03-29 20:37:22 -05:00 |
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RISCVSubtarget.cpp
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[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
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2021-04-23 15:06:20 -07:00 |
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RISCVSubtarget.h
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[RISCV] Enable interleaved vectorization for RVV
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2021-05-29 11:03:27 +08:00 |
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RISCVSystemOperands.td
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RISCV: add a few deprecated aliases for CSRs
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2021-05-21 13:52:58 -07:00 |
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RISCVTargetMachine.cpp
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[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
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2021-05-24 11:47:27 -07:00 |
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
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2021-02-26 16:38:44 -08:00 |
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Add support for fmin/fmax vector reductions
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2021-05-03 10:33:51 +01:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Expand unaligned fixed-length vector memory accesses
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2021-06-02 09:27:44 +01:00 |
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