forked from OSchip/llvm-project
1180 lines
40 KiB
C++
1180 lines
40 KiB
C++
//===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file Methods common to all machine operands.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/ADT/FoldingSet.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Analysis/Loads.h"
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#include "llvm/Analysis/MemoryLocation.h"
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#include "llvm/CodeGen/MIRFormatter.h"
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#include "llvm/CodeGen/MIRPrinter.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/Config/llvm-config.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/IRPrintingPasses.h"
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#include "llvm/IR/ModuleSlotTracker.h"
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#include "llvm/MC/MCDwarf.h"
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#include "llvm/Target/TargetIntrinsicInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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static cl::opt<int>
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PrintRegMaskNumRegs("print-regmask-num-regs",
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cl::desc("Number of registers to limit to when "
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"printing regmask operands in IR dumps. "
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"unlimited = -1"),
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cl::init(32), cl::Hidden);
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static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
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if (const MachineInstr *MI = MO.getParent())
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if (const MachineBasicBlock *MBB = MI->getParent())
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if (const MachineFunction *MF = MBB->getParent())
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return MF;
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return nullptr;
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}
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static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
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return const_cast<MachineFunction *>(
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getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
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}
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void MachineOperand::setReg(Register Reg) {
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if (getReg() == Reg)
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return; // No change.
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// Clear the IsRenamable bit to keep it conservatively correct.
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IsRenamable = false;
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// Otherwise, we have to change the register. If this operand is embedded
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// into a machine function, we need to update the old and new register's
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// use/def lists.
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if (MachineFunction *MF = getMFIfAvailable(*this)) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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MRI.removeRegOperandFromUseList(this);
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SmallContents.RegNo = Reg;
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MRI.addRegOperandToUseList(this);
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return;
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}
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// Otherwise, just change the register, no problem. :)
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SmallContents.RegNo = Reg;
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}
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void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
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const TargetRegisterInfo &TRI) {
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assert(Reg.isVirtual());
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if (SubIdx && getSubReg())
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SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
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setReg(Reg);
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if (SubIdx)
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setSubReg(SubIdx);
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}
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void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
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assert(Reg.isPhysical());
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if (getSubReg()) {
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Reg = TRI.getSubReg(Reg, getSubReg());
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// Note that getSubReg() may return 0 if the sub-register doesn't exist.
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// That won't happen in legal code.
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setSubReg(0);
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if (isDef())
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setIsUndef(false);
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}
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setReg(Reg);
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}
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/// Change a def to a use, or a use to a def.
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void MachineOperand::setIsDef(bool Val) {
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assert(isReg() && "Wrong MachineOperand accessor");
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assert((!Val || !isDebug()) && "Marking a debug operation as def");
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if (IsDef == Val)
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return;
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assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
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// MRI may keep uses and defs in different list positions.
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if (MachineFunction *MF = getMFIfAvailable(*this)) {
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MachineRegisterInfo &MRI = MF->getRegInfo();
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MRI.removeRegOperandFromUseList(this);
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IsDef = Val;
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MRI.addRegOperandToUseList(this);
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return;
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}
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IsDef = Val;
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}
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bool MachineOperand::isRenamable() const {
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assert(isReg() && "Wrong MachineOperand accessor");
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assert(Register::isPhysicalRegister(getReg()) &&
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"isRenamable should only be checked on physical registers");
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if (!IsRenamable)
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return false;
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const MachineInstr *MI = getParent();
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if (!MI)
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return true;
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if (isDef())
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return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
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assert(isUse() && "Reg is not def or use");
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return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
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}
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void MachineOperand::setIsRenamable(bool Val) {
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assert(isReg() && "Wrong MachineOperand accessor");
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assert(Register::isPhysicalRegister(getReg()) &&
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"setIsRenamable should only be called on physical registers");
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IsRenamable = Val;
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}
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// If this operand is currently a register operand, and if this is in a
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// function, deregister the operand from the register's use/def list.
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void MachineOperand::removeRegFromUses() {
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if (!isReg() || !isOnRegUseList())
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return;
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if (MachineFunction *MF = getMFIfAvailable(*this))
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MF->getRegInfo().removeRegOperandFromUseList(this);
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}
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImm method should be used.
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void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
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assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
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removeRegFromUses();
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OpKind = MO_Immediate;
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Contents.ImmVal = ImmVal;
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}
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void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
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assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
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removeRegFromUses();
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OpKind = MO_FPImmediate;
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Contents.CFP = FPImm;
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}
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void MachineOperand::ChangeToES(const char *SymName,
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unsigned TargetFlags) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into an external symbol");
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removeRegFromUses();
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OpKind = MO_ExternalSymbol;
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Contents.OffsetedInfo.Val.SymbolName = SymName;
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setOffset(0); // Offset is always 0.
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setTargetFlags(TargetFlags);
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}
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void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
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unsigned TargetFlags) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into a global address");
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removeRegFromUses();
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OpKind = MO_GlobalAddress;
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Contents.OffsetedInfo.Val.GV = GV;
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setOffset(Offset);
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setTargetFlags(TargetFlags);
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}
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void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into an MCSymbol");
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removeRegFromUses();
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OpKind = MO_MCSymbol;
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Contents.Sym = Sym;
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}
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void MachineOperand::ChangeToFrameIndex(int Idx) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into a FrameIndex");
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removeRegFromUses();
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OpKind = MO_FrameIndex;
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setIndex(Idx);
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}
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void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
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unsigned TargetFlags) {
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assert((!isReg() || !isTied()) &&
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"Cannot change a tied operand into a FrameIndex");
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removeRegFromUses();
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OpKind = MO_TargetIndex;
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setIndex(Idx);
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setOffset(Offset);
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setTargetFlags(TargetFlags);
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}
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/// ChangeToRegister - Replace this operand with a new register operand of
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
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bool isKill, bool isDead, bool isUndef,
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bool isDebug) {
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MachineRegisterInfo *RegInfo = nullptr;
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if (MachineFunction *MF = getMFIfAvailable(*this))
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RegInfo = &MF->getRegInfo();
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// If this operand is already a register operand, remove it from the
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// register's use/def lists.
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bool WasReg = isReg();
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if (RegInfo && WasReg)
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RegInfo->removeRegOperandFromUseList(this);
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// Change this to a register and set the reg#.
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assert(!(isDead && !isDef) && "Dead flag on non-def");
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assert(!(isKill && isDef) && "Kill flag on def");
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OpKind = MO_Register;
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SmallContents.RegNo = Reg;
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SubReg_TargetFlags = 0;
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IsDef = isDef;
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IsImp = isImp;
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IsDeadOrKill = isKill | isDead;
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IsRenamable = false;
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IsUndef = isUndef;
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IsInternalRead = false;
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IsEarlyClobber = false;
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IsDebug = isDebug;
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// Ensure isOnRegUseList() returns false.
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Contents.Reg.Prev = nullptr;
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// Preserve the tie when the operand was already a register.
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if (!WasReg)
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TiedTo = 0;
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// If this operand is embedded in a function, add the operand to the
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// register's use/def list.
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if (RegInfo)
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RegInfo->addRegOperandToUseList(this);
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}
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand. Note that this should stay in sync with the hash_value overload
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/// below.
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType() ||
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getTargetFlags() != Other.getTargetFlags())
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return false;
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switch (getType()) {
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case MachineOperand::MO_Register:
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return getReg() == Other.getReg() && isDef() == Other.isDef() &&
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getSubReg() == Other.getSubReg();
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case MachineOperand::MO_Immediate:
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return getImm() == Other.getImm();
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case MachineOperand::MO_CImmediate:
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return getCImm() == Other.getCImm();
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case MachineOperand::MO_FPImmediate:
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return getFPImm() == Other.getFPImm();
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case MachineOperand::MO_MachineBasicBlock:
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return getMBB() == Other.getMBB();
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case MachineOperand::MO_FrameIndex:
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return getIndex() == Other.getIndex();
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_TargetIndex:
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return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
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case MachineOperand::MO_JumpTableIndex:
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return getIndex() == Other.getIndex();
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case MachineOperand::MO_GlobalAddress:
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return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
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case MachineOperand::MO_ExternalSymbol:
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return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
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getOffset() == Other.getOffset();
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case MachineOperand::MO_BlockAddress:
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return getBlockAddress() == Other.getBlockAddress() &&
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getOffset() == Other.getOffset();
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case MachineOperand::MO_RegisterMask:
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case MachineOperand::MO_RegisterLiveOut: {
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// Shallow compare of the two RegMasks
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const uint32_t *RegMask = getRegMask();
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const uint32_t *OtherRegMask = Other.getRegMask();
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if (RegMask == OtherRegMask)
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return true;
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if (const MachineFunction *MF = getMFIfAvailable(*this)) {
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// Calculate the size of the RegMask
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
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// Deep compare of the two RegMasks
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return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
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}
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// We don't know the size of the RegMask, so we can't deep compare the two
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// reg masks.
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return false;
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}
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case MachineOperand::MO_MCSymbol:
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return getMCSymbol() == Other.getMCSymbol();
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case MachineOperand::MO_CFIIndex:
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return getCFIIndex() == Other.getCFIIndex();
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case MachineOperand::MO_Metadata:
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return getMetadata() == Other.getMetadata();
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case MachineOperand::MO_IntrinsicID:
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return getIntrinsicID() == Other.getIntrinsicID();
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case MachineOperand::MO_Predicate:
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return getPredicate() == Other.getPredicate();
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case MachineOperand::MO_ShuffleMask:
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return getShuffleMask() == Other.getShuffleMask();
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}
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llvm_unreachable("Invalid machine operand type");
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}
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// Note: this must stay exactly in sync with isIdenticalTo above.
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hash_code llvm::hash_value(const MachineOperand &MO) {
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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// Register operands don't have target flags.
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return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
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case MachineOperand::MO_Immediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
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case MachineOperand::MO_CImmediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
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case MachineOperand::MO_FPImmediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
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case MachineOperand::MO_MachineBasicBlock:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
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case MachineOperand::MO_FrameIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_TargetIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
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MO.getOffset());
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case MachineOperand::MO_JumpTableIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
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case MachineOperand::MO_ExternalSymbol:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
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StringRef(MO.getSymbolName()));
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case MachineOperand::MO_GlobalAddress:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
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MO.getOffset());
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case MachineOperand::MO_BlockAddress:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
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MO.getOffset());
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case MachineOperand::MO_RegisterMask:
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case MachineOperand::MO_RegisterLiveOut:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
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case MachineOperand::MO_Metadata:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
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case MachineOperand::MO_MCSymbol:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
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case MachineOperand::MO_CFIIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
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case MachineOperand::MO_IntrinsicID:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
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case MachineOperand::MO_Predicate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
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case MachineOperand::MO_ShuffleMask:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
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}
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llvm_unreachable("Invalid machine operand type");
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}
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// Try to crawl up to the machine function and get TRI and IntrinsicInfo from
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// it.
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static void tryToGetTargetInfo(const MachineOperand &MO,
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const TargetRegisterInfo *&TRI,
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const TargetIntrinsicInfo *&IntrinsicInfo) {
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if (const MachineFunction *MF = getMFIfAvailable(MO)) {
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TRI = MF->getSubtarget().getRegisterInfo();
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IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
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}
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}
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static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
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const auto *TII = MF.getSubtarget().getInstrInfo();
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assert(TII && "expected instruction info");
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auto Indices = TII->getSerializableTargetIndices();
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auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
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return I.first == Index;
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});
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if (Found != Indices.end())
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return Found->second;
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return nullptr;
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}
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static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
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auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
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for (const auto &I : Flags) {
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if (I.first == TF) {
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return I.second;
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}
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}
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return nullptr;
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}
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static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
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const TargetRegisterInfo *TRI) {
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if (!TRI) {
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OS << "%dwarfreg." << DwarfReg;
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return;
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}
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if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
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OS << printReg(*Reg, TRI);
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else
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OS << "<badreg>";
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}
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static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
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ModuleSlotTracker &MST) {
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OS << "%ir-block.";
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if (BB.hasName()) {
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printLLVMNameWithoutPrefix(OS, BB.getName());
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return;
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}
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Optional<int> Slot;
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if (const Function *F = BB.getParent()) {
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if (F == MST.getCurrentFunction()) {
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Slot = MST.getLocalSlot(&BB);
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} else if (const Module *M = F->getParent()) {
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ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
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CustomMST.incorporateFunction(*F);
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Slot = CustomMST.getLocalSlot(&BB);
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}
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}
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if (Slot)
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MachineOperand::printIRSlotNumber(OS, *Slot);
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else
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OS << "<unknown>";
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}
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static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
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SyncScope::ID SSID,
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SmallVectorImpl<StringRef> &SSNs) {
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switch (SSID) {
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case SyncScope::System:
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break;
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default:
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if (SSNs.empty())
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Context.getSyncScopeNames(SSNs);
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OS << "syncscope(\"";
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printEscapedString(SSNs[SSID], OS);
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OS << "\") ";
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break;
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}
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}
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|
|
static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
|
|
unsigned TMMOFlag) {
|
|
auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
|
|
for (const auto &I : Flags) {
|
|
if (I.first == TMMOFlag) {
|
|
return I.second;
|
|
}
|
|
}
|
|
return nullptr;
|
|
}
|
|
|
|
static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
|
|
const MachineFrameInfo *MFI) {
|
|
StringRef Name;
|
|
if (MFI) {
|
|
IsFixed = MFI->isFixedObjectIndex(FrameIndex);
|
|
if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
|
|
if (Alloca->hasName())
|
|
Name = Alloca->getName();
|
|
if (IsFixed)
|
|
FrameIndex -= MFI->getObjectIndexBegin();
|
|
}
|
|
MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
|
|
}
|
|
|
|
void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
|
|
const TargetRegisterInfo *TRI) {
|
|
OS << "%subreg.";
|
|
if (TRI)
|
|
OS << TRI->getSubRegIndexName(Index);
|
|
else
|
|
OS << Index;
|
|
}
|
|
|
|
void MachineOperand::printTargetFlags(raw_ostream &OS,
|
|
const MachineOperand &Op) {
|
|
if (!Op.getTargetFlags())
|
|
return;
|
|
const MachineFunction *MF = getMFIfAvailable(Op);
|
|
if (!MF)
|
|
return;
|
|
|
|
const auto *TII = MF->getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
|
|
OS << "target-flags(";
|
|
const bool HasDirectFlags = Flags.first;
|
|
const bool HasBitmaskFlags = Flags.second;
|
|
if (!HasDirectFlags && !HasBitmaskFlags) {
|
|
OS << "<unknown>) ";
|
|
return;
|
|
}
|
|
if (HasDirectFlags) {
|
|
if (const auto *Name = getTargetFlagName(TII, Flags.first))
|
|
OS << Name;
|
|
else
|
|
OS << "<unknown target flag>";
|
|
}
|
|
if (!HasBitmaskFlags) {
|
|
OS << ") ";
|
|
return;
|
|
}
|
|
bool IsCommaNeeded = HasDirectFlags;
|
|
unsigned BitMask = Flags.second;
|
|
auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
|
|
for (const auto &Mask : BitMasks) {
|
|
// Check if the flag's bitmask has the bits of the current mask set.
|
|
if ((BitMask & Mask.first) == Mask.first) {
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
IsCommaNeeded = true;
|
|
OS << Mask.second;
|
|
// Clear the bits which were serialized from the flag's bitmask.
|
|
BitMask &= ~(Mask.first);
|
|
}
|
|
}
|
|
if (BitMask) {
|
|
// When the resulting flag's bitmask isn't zero, we know that we didn't
|
|
// serialize all of the bit flags.
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
OS << "<unknown bitmask target flag>";
|
|
}
|
|
OS << ") ";
|
|
}
|
|
|
|
void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
|
|
OS << "<mcsymbol " << Sym << ">";
|
|
}
|
|
|
|
void MachineOperand::printStackObjectReference(raw_ostream &OS,
|
|
unsigned FrameIndex,
|
|
bool IsFixed, StringRef Name) {
|
|
if (IsFixed) {
|
|
OS << "%fixed-stack." << FrameIndex;
|
|
return;
|
|
}
|
|
|
|
OS << "%stack." << FrameIndex;
|
|
if (!Name.empty())
|
|
OS << '.' << Name;
|
|
}
|
|
|
|
void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
|
|
if (Offset == 0)
|
|
return;
|
|
if (Offset < 0) {
|
|
OS << " - " << -Offset;
|
|
return;
|
|
}
|
|
OS << " + " << Offset;
|
|
}
|
|
|
|
void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
|
|
if (Slot == -1)
|
|
OS << "<badref>";
|
|
else
|
|
OS << Slot;
|
|
}
|
|
|
|
static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
|
|
const TargetRegisterInfo *TRI) {
|
|
switch (CFI.getOperation()) {
|
|
case MCCFIInstruction::OpSameValue:
|
|
OS << "same_value ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpRememberState:
|
|
OS << "remember_state ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
break;
|
|
case MCCFIInstruction::OpRestoreState:
|
|
OS << "restore_state ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
break;
|
|
case MCCFIInstruction::OpOffset:
|
|
OS << "offset ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaRegister:
|
|
OS << "def_cfa_register ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpDefCfaOffset:
|
|
OS << "def_cfa_offset ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
OS << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpDefCfa:
|
|
OS << "def_cfa ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpRelOffset:
|
|
OS << "rel_offset ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", " << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpAdjustCfaOffset:
|
|
OS << "adjust_cfa_offset ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
OS << CFI.getOffset();
|
|
break;
|
|
case MCCFIInstruction::OpRestore:
|
|
OS << "restore ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpEscape: {
|
|
OS << "escape ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
if (!CFI.getValues().empty()) {
|
|
size_t e = CFI.getValues().size() - 1;
|
|
for (size_t i = 0; i < e; ++i)
|
|
OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
|
|
OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
|
|
}
|
|
break;
|
|
}
|
|
case MCCFIInstruction::OpUndefined:
|
|
OS << "undefined ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpRegister:
|
|
OS << "register ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
printCFIRegister(CFI.getRegister(), OS, TRI);
|
|
OS << ", ";
|
|
printCFIRegister(CFI.getRegister2(), OS, TRI);
|
|
break;
|
|
case MCCFIInstruction::OpWindowSave:
|
|
OS << "window_save ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
break;
|
|
case MCCFIInstruction::OpNegateRAState:
|
|
OS << "negate_ra_sign_state ";
|
|
if (MCSymbol *Label = CFI.getLabel())
|
|
MachineOperand::printSymbol(OS, *Label);
|
|
break;
|
|
default:
|
|
// TODO: Print the other CFI Operations.
|
|
OS << "<unserializable cfi directive>";
|
|
break;
|
|
}
|
|
}
|
|
|
|
void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
|
|
const TargetIntrinsicInfo *IntrinsicInfo) const {
|
|
print(OS, LLT{}, TRI, IntrinsicInfo);
|
|
}
|
|
|
|
void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
|
|
const TargetRegisterInfo *TRI,
|
|
const TargetIntrinsicInfo *IntrinsicInfo) const {
|
|
tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
|
|
ModuleSlotTracker DummyMST(nullptr);
|
|
print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
|
|
/*IsStandalone=*/true,
|
|
/*ShouldPrintRegisterTies=*/true,
|
|
/*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
|
|
}
|
|
|
|
void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
|
|
LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
|
|
bool IsStandalone, bool ShouldPrintRegisterTies,
|
|
unsigned TiedOperandIdx,
|
|
const TargetRegisterInfo *TRI,
|
|
const TargetIntrinsicInfo *IntrinsicInfo) const {
|
|
printTargetFlags(OS, *this);
|
|
switch (getType()) {
|
|
case MachineOperand::MO_Register: {
|
|
Register Reg = getReg();
|
|
if (isImplicit())
|
|
OS << (isDef() ? "implicit-def " : "implicit ");
|
|
else if (PrintDef && isDef())
|
|
// Print the 'def' flag only when the operand is defined after '='.
|
|
OS << "def ";
|
|
if (isInternalRead())
|
|
OS << "internal ";
|
|
if (isDead())
|
|
OS << "dead ";
|
|
if (isKill())
|
|
OS << "killed ";
|
|
if (isUndef())
|
|
OS << "undef ";
|
|
if (isEarlyClobber())
|
|
OS << "early-clobber ";
|
|
if (Register::isPhysicalRegister(getReg()) && isRenamable())
|
|
OS << "renamable ";
|
|
// isDebug() is exactly true for register operands of a DBG_VALUE. So we
|
|
// simply infer it when parsing and do not need to print it.
|
|
|
|
const MachineRegisterInfo *MRI = nullptr;
|
|
if (Register::isVirtualRegister(Reg)) {
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
|
|
MRI = &MF->getRegInfo();
|
|
}
|
|
}
|
|
|
|
OS << printReg(Reg, TRI, 0, MRI);
|
|
// Print the sub register.
|
|
if (unsigned SubReg = getSubReg()) {
|
|
if (TRI)
|
|
OS << '.' << TRI->getSubRegIndexName(SubReg);
|
|
else
|
|
OS << ".subreg" << SubReg;
|
|
}
|
|
// Print the register class / bank.
|
|
if (Register::isVirtualRegister(Reg)) {
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
|
|
const MachineRegisterInfo &MRI = MF->getRegInfo();
|
|
if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
|
|
OS << ':';
|
|
OS << printRegClassOrBank(Reg, MRI, TRI);
|
|
}
|
|
}
|
|
}
|
|
// Print ties.
|
|
if (ShouldPrintRegisterTies && isTied() && !isDef())
|
|
OS << "(tied-def " << TiedOperandIdx << ")";
|
|
// Print types.
|
|
if (TypeToPrint.isValid())
|
|
OS << '(' << TypeToPrint << ')';
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Immediate: {
|
|
const MIRFormatter *Formatter = nullptr;
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this)) {
|
|
const auto *TII = MF->getSubtarget().getInstrInfo();
|
|
assert(TII && "expected instruction info");
|
|
Formatter = TII->getMIRFormatter();
|
|
}
|
|
if (Formatter)
|
|
Formatter->printImm(OS, *getParent(), OpIdx, getImm());
|
|
else
|
|
OS << getImm();
|
|
break;
|
|
}
|
|
case MachineOperand::MO_CImmediate:
|
|
getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_FPImmediate:
|
|
getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
|
|
break;
|
|
case MachineOperand::MO_MachineBasicBlock:
|
|
OS << printMBBReference(*getMBB());
|
|
break;
|
|
case MachineOperand::MO_FrameIndex: {
|
|
int FrameIndex = getIndex();
|
|
bool IsFixed = false;
|
|
const MachineFrameInfo *MFI = nullptr;
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this))
|
|
MFI = &MF->getFrameInfo();
|
|
printFrameIndex(OS, FrameIndex, IsFixed, MFI);
|
|
break;
|
|
}
|
|
case MachineOperand::MO_ConstantPoolIndex:
|
|
OS << "%const." << getIndex();
|
|
printOperandOffset(OS, getOffset());
|
|
break;
|
|
case MachineOperand::MO_TargetIndex: {
|
|
OS << "target-index(";
|
|
const char *Name = "<unknown>";
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this))
|
|
if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
|
|
Name = TargetIndexName;
|
|
OS << Name << ')';
|
|
printOperandOffset(OS, getOffset());
|
|
break;
|
|
}
|
|
case MachineOperand::MO_JumpTableIndex:
|
|
OS << printJumpTableEntryReference(getIndex());
|
|
break;
|
|
case MachineOperand::MO_GlobalAddress:
|
|
getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
|
|
printOperandOffset(OS, getOffset());
|
|
break;
|
|
case MachineOperand::MO_ExternalSymbol: {
|
|
StringRef Name = getSymbolName();
|
|
OS << '&';
|
|
if (Name.empty()) {
|
|
OS << "\"\"";
|
|
} else {
|
|
printLLVMNameWithoutPrefix(OS, Name);
|
|
}
|
|
printOperandOffset(OS, getOffset());
|
|
break;
|
|
}
|
|
case MachineOperand::MO_BlockAddress: {
|
|
OS << "blockaddress(";
|
|
getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
|
|
MST);
|
|
OS << ", ";
|
|
printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
|
|
OS << ')';
|
|
MachineOperand::printOperandOffset(OS, getOffset());
|
|
break;
|
|
}
|
|
case MachineOperand::MO_RegisterMask: {
|
|
OS << "<regmask";
|
|
if (TRI) {
|
|
unsigned NumRegsInMask = 0;
|
|
unsigned NumRegsEmitted = 0;
|
|
for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
|
|
unsigned MaskWord = i / 32;
|
|
unsigned MaskBit = i % 32;
|
|
if (getRegMask()[MaskWord] & (1 << MaskBit)) {
|
|
if (PrintRegMaskNumRegs < 0 ||
|
|
NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
|
|
OS << " " << printReg(i, TRI);
|
|
NumRegsEmitted++;
|
|
}
|
|
NumRegsInMask++;
|
|
}
|
|
}
|
|
if (NumRegsEmitted != NumRegsInMask)
|
|
OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
|
|
} else {
|
|
OS << " ...";
|
|
}
|
|
OS << ">";
|
|
break;
|
|
}
|
|
case MachineOperand::MO_RegisterLiveOut: {
|
|
const uint32_t *RegMask = getRegLiveOut();
|
|
OS << "liveout(";
|
|
if (!TRI) {
|
|
OS << "<unknown>";
|
|
} else {
|
|
bool IsCommaNeeded = false;
|
|
for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
|
|
if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
|
|
if (IsCommaNeeded)
|
|
OS << ", ";
|
|
OS << printReg(Reg, TRI);
|
|
IsCommaNeeded = true;
|
|
}
|
|
}
|
|
}
|
|
OS << ")";
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Metadata:
|
|
getMetadata()->printAsOperand(OS, MST);
|
|
break;
|
|
case MachineOperand::MO_MCSymbol:
|
|
printSymbol(OS, *getMCSymbol());
|
|
break;
|
|
case MachineOperand::MO_CFIIndex: {
|
|
if (const MachineFunction *MF = getMFIfAvailable(*this))
|
|
printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
|
|
else
|
|
OS << "<cfi directive>";
|
|
break;
|
|
}
|
|
case MachineOperand::MO_IntrinsicID: {
|
|
Intrinsic::ID ID = getIntrinsicID();
|
|
if (ID < Intrinsic::num_intrinsics)
|
|
OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
|
|
else if (IntrinsicInfo)
|
|
OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
|
|
else
|
|
OS << "intrinsic(" << ID << ')';
|
|
break;
|
|
}
|
|
case MachineOperand::MO_Predicate: {
|
|
auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
|
|
OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
|
|
<< CmpInst::getPredicateName(Pred) << ')';
|
|
break;
|
|
}
|
|
case MachineOperand::MO_ShuffleMask:
|
|
OS << "shufflemask(";
|
|
ArrayRef<int> Mask = getShuffleMask();
|
|
StringRef Separator;
|
|
for (int Elt : Mask) {
|
|
if (Elt == -1)
|
|
OS << Separator << "undef";
|
|
else
|
|
OS << Separator << Elt;
|
|
Separator = ", ";
|
|
}
|
|
|
|
OS << ')';
|
|
break;
|
|
}
|
|
}
|
|
|
|
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
|
LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
|
|
#endif
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MachineMemOperand Implementation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// getAddrSpace - Return the LLVM IR address space number that this pointer
|
|
/// points into.
|
|
unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
|
|
|
|
/// isDereferenceable - Return true if V is always dereferenceable for
|
|
/// Offset + Size byte.
|
|
bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
|
|
const DataLayout &DL) const {
|
|
if (!V.is<const Value *>())
|
|
return false;
|
|
|
|
const Value *BasePtr = V.get<const Value *>();
|
|
if (BasePtr == nullptr)
|
|
return false;
|
|
|
|
return isDereferenceableAndAlignedPointer(
|
|
BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
|
|
}
|
|
|
|
/// getConstantPool - Return a MachinePointerInfo record that refers to the
|
|
/// constant pool.
|
|
MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
|
|
return MachinePointerInfo(MF.getPSVManager().getConstantPool());
|
|
}
|
|
|
|
/// getFixedStack - Return a MachinePointerInfo record that refers to the
|
|
/// the specified FrameIndex.
|
|
MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
|
|
int FI, int64_t Offset) {
|
|
return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
|
|
}
|
|
|
|
MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
|
|
return MachinePointerInfo(MF.getPSVManager().getJumpTable());
|
|
}
|
|
|
|
MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
|
|
return MachinePointerInfo(MF.getPSVManager().getGOT());
|
|
}
|
|
|
|
MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
|
|
int64_t Offset, uint8_t ID) {
|
|
return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
|
|
}
|
|
|
|
MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
|
|
return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
|
|
}
|
|
|
|
MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
|
|
uint64_t s, Align a,
|
|
const AAMDNodes &AAInfo,
|
|
const MDNode *Ranges, SyncScope::ID SSID,
|
|
AtomicOrdering Ordering,
|
|
AtomicOrdering FailureOrdering)
|
|
: PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlign(a), AAInfo(AAInfo),
|
|
Ranges(Ranges) {
|
|
assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
|
|
isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
|
|
"invalid pointer value");
|
|
assert((isLoad() || isStore()) && "Not a load/store!");
|
|
|
|
AtomicInfo.SSID = static_cast<unsigned>(SSID);
|
|
assert(getSyncScopeID() == SSID && "Value truncated");
|
|
AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
|
|
assert(getOrdering() == Ordering && "Value truncated");
|
|
AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
|
|
assert(getFailureOrdering() == FailureOrdering && "Value truncated");
|
|
}
|
|
|
|
/// Profile - Gather unique data for the object.
|
|
///
|
|
void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
|
|
ID.AddInteger(getOffset());
|
|
ID.AddInteger(Size);
|
|
ID.AddPointer(getOpaqueValue());
|
|
ID.AddInteger(getFlags());
|
|
ID.AddInteger(getBaseAlign().value());
|
|
}
|
|
|
|
void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
|
|
// The Value and Offset may differ due to CSE. But the flags and size
|
|
// should be the same.
|
|
assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
|
|
assert(MMO->getSize() == getSize() && "Size mismatch!");
|
|
|
|
if (MMO->getBaseAlign() >= getBaseAlign()) {
|
|
// Update the alignment value.
|
|
BaseAlign = MMO->getBaseAlign();
|
|
// Also update the base and offset, because the new alignment may
|
|
// not be applicable with the old ones.
|
|
PtrInfo = MMO->PtrInfo;
|
|
}
|
|
}
|
|
|
|
/// getAlignment - Return the minimum known alignment in bytes of the
|
|
/// actual memory reference.
|
|
uint64_t MachineMemOperand::getAlignment() const { return getAlign().value(); }
|
|
|
|
/// getAlign - Return the minimum known alignment in bytes of the
|
|
/// actual memory reference.
|
|
Align MachineMemOperand::getAlign() const {
|
|
return commonAlignment(getBaseAlign(), getOffset());
|
|
}
|
|
|
|
void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
|
|
SmallVectorImpl<StringRef> &SSNs,
|
|
const LLVMContext &Context,
|
|
const MachineFrameInfo *MFI,
|
|
const TargetInstrInfo *TII) const {
|
|
OS << '(';
|
|
if (isVolatile())
|
|
OS << "volatile ";
|
|
if (isNonTemporal())
|
|
OS << "non-temporal ";
|
|
if (isDereferenceable())
|
|
OS << "dereferenceable ";
|
|
if (isInvariant())
|
|
OS << "invariant ";
|
|
if (getFlags() & MachineMemOperand::MOTargetFlag1)
|
|
OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
|
|
<< "\" ";
|
|
if (getFlags() & MachineMemOperand::MOTargetFlag2)
|
|
OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
|
|
<< "\" ";
|
|
if (getFlags() & MachineMemOperand::MOTargetFlag3)
|
|
OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
|
|
<< "\" ";
|
|
|
|
assert((isLoad() || isStore()) &&
|
|
"machine memory operand must be a load or store (or both)");
|
|
if (isLoad())
|
|
OS << "load ";
|
|
if (isStore())
|
|
OS << "store ";
|
|
|
|
printSyncScope(OS, Context, getSyncScopeID(), SSNs);
|
|
|
|
if (getOrdering() != AtomicOrdering::NotAtomic)
|
|
OS << toIRString(getOrdering()) << ' ';
|
|
if (getFailureOrdering() != AtomicOrdering::NotAtomic)
|
|
OS << toIRString(getFailureOrdering()) << ' ';
|
|
|
|
if (getSize() == MemoryLocation::UnknownSize)
|
|
OS << "unknown-size";
|
|
else
|
|
OS << getSize();
|
|
|
|
if (const Value *Val = getValue()) {
|
|
OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
|
|
MIRFormatter::printIRValue(OS, *Val, MST);
|
|
} else if (const PseudoSourceValue *PVal = getPseudoValue()) {
|
|
OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
|
|
assert(PVal && "Expected a pseudo source value");
|
|
switch (PVal->kind()) {
|
|
case PseudoSourceValue::Stack:
|
|
OS << "stack";
|
|
break;
|
|
case PseudoSourceValue::GOT:
|
|
OS << "got";
|
|
break;
|
|
case PseudoSourceValue::JumpTable:
|
|
OS << "jump-table";
|
|
break;
|
|
case PseudoSourceValue::ConstantPool:
|
|
OS << "constant-pool";
|
|
break;
|
|
case PseudoSourceValue::FixedStack: {
|
|
int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
|
|
bool IsFixed = true;
|
|
printFrameIndex(OS, FrameIndex, IsFixed, MFI);
|
|
break;
|
|
}
|
|
case PseudoSourceValue::GlobalValueCallEntry:
|
|
OS << "call-entry ";
|
|
cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
|
|
OS, /*PrintType=*/false, MST);
|
|
break;
|
|
case PseudoSourceValue::ExternalSymbolCallEntry:
|
|
OS << "call-entry &";
|
|
printLLVMNameWithoutPrefix(
|
|
OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
|
|
break;
|
|
default: {
|
|
const MIRFormatter *Formatter = TII->getMIRFormatter();
|
|
// FIXME: This is not necessarily the correct MIR serialization format for
|
|
// a custom pseudo source value, but at least it allows
|
|
// -print-machineinstrs to work on a target with custom pseudo source
|
|
// values.
|
|
OS << "custom \"";
|
|
Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
|
|
OS << '\"';
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
MachineOperand::printOperandOffset(OS, getOffset());
|
|
if (getBaseAlign() != getSize())
|
|
OS << ", align " << getBaseAlign().value();
|
|
auto AAInfo = getAAInfo();
|
|
if (AAInfo.TBAA) {
|
|
OS << ", !tbaa ";
|
|
AAInfo.TBAA->printAsOperand(OS, MST);
|
|
}
|
|
if (AAInfo.Scope) {
|
|
OS << ", !alias.scope ";
|
|
AAInfo.Scope->printAsOperand(OS, MST);
|
|
}
|
|
if (AAInfo.NoAlias) {
|
|
OS << ", !noalias ";
|
|
AAInfo.NoAlias->printAsOperand(OS, MST);
|
|
}
|
|
if (getRanges()) {
|
|
OS << ", !range ";
|
|
getRanges()->printAsOperand(OS, MST);
|
|
}
|
|
// FIXME: Implement addrspace printing/parsing in MIR.
|
|
// For now, print this even though parsing it is not available in MIR.
|
|
if (unsigned AS = getAddrSpace())
|
|
OS << ", addrspace " << AS;
|
|
|
|
OS << ')';
|
|
}
|