forked from OSchip/llvm-project
312 lines
11 KiB
C++
312 lines
11 KiB
C++
//===-- FixupStatepointCallerSaved.cpp - Fixup caller saved registers ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Statepoint instruction in deopt parameters contains values which are
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/// meaningful to the runtime and should be able to be read at the moment the
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/// call returns. So we can say that we need to encode the fact that these
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/// values are "late read" by runtime. If we could express this notion for
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/// register allocator it would produce the right form for us.
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/// The need to fixup (i.e this pass) is specifically handling the fact that
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/// we cannot describe such a late read for the register allocator.
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/// Register allocator may put the value on a register clobbered by the call.
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/// This pass forces the spill of such registers and replaces corresponding
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/// statepoint operands to added spill slots.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Statepoint.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "fixup-statepoint-caller-saved"
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STATISTIC(NumSpilledRegisters, "Number of spilled register");
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STATISTIC(NumSpillSlotsAllocated, "Number of spill slots allocated");
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STATISTIC(NumSpillSlotsExtended, "Number of spill slots extended");
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static cl::opt<bool> FixupSCSExtendSlotSize(
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"fixup-scs-extend-slot-size", cl::Hidden, cl::init(false),
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cl::desc("Allow spill in spill slot of greater size than register size"),
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cl::Hidden);
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namespace {
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class FixupStatepointCallerSaved : public MachineFunctionPass {
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public:
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static char ID;
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FixupStatepointCallerSaved() : MachineFunctionPass(ID) {
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initializeFixupStatepointCallerSavedPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return "Fixup Statepoint Caller Saved";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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};
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} // End anonymous namespace.
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char FixupStatepointCallerSaved::ID = 0;
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char &llvm::FixupStatepointCallerSavedID = FixupStatepointCallerSaved::ID;
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INITIALIZE_PASS_BEGIN(FixupStatepointCallerSaved, DEBUG_TYPE,
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"Fixup Statepoint Caller Saved", false, false)
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INITIALIZE_PASS_END(FixupStatepointCallerSaved, DEBUG_TYPE,
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"Fixup Statepoint Caller Saved", false, false)
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// Utility function to get size of the register.
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static unsigned getRegisterSize(const TargetRegisterInfo &TRI, Register Reg) {
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
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return TRI.getSpillSize(*RC);
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}
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namespace {
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// Cache used frame indexes during statepoint re-write to re-use them in
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// processing next statepoint instruction.
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// Two strategies. One is to preserve the size of spill slot while another one
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// extends the size of spill slots to reduce the number of them, causing
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// the less total frame size. But unspill will have "implicit" any extend.
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class FrameIndexesCache {
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private:
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struct FrameIndexesPerSize {
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// List of used frame indexes during processing previous statepoints.
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SmallVector<int, 8> Slots;
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// Current index of un-used yet frame index.
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unsigned Index = 0;
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};
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MachineFrameInfo &MFI;
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const TargetRegisterInfo &TRI;
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// Map size to list of frame indexes of this size. If the mode is
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// FixupSCSExtendSlotSize then the key 0 is used to keep all frame indexes.
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// If the size of required spill slot is greater than in a cache then the
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// size will be increased.
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DenseMap<unsigned, FrameIndexesPerSize> Cache;
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public:
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FrameIndexesCache(MachineFrameInfo &MFI, const TargetRegisterInfo &TRI)
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: MFI(MFI), TRI(TRI) {}
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// Reset the current state of used frame indexes. After invocation of
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// this function all frame indexes are available for allocation.
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void reset() {
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for (auto &It : Cache)
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It.second.Index = 0;
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}
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// Get frame index to spill the register.
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int getFrameIndex(Register Reg) {
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unsigned Size = getRegisterSize(TRI, Reg);
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// In FixupSCSExtendSlotSize mode the bucket with 0 index is used
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// for all sizes.
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unsigned Bucket = FixupSCSExtendSlotSize ? 0 : Size;
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FrameIndexesPerSize &Line = Cache[Bucket];
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if (Line.Index < Line.Slots.size()) {
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int FI = Line.Slots[Line.Index++];
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// If all sizes are kept together we probably need to extend the
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// spill slot size.
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if (MFI.getObjectSize(FI) < Size) {
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MFI.setObjectSize(FI, Size);
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MFI.setObjectAlignment(FI, Align(Size));
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NumSpillSlotsExtended++;
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}
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return FI;
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}
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int FI = MFI.CreateSpillStackObject(Size, Size);
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NumSpillSlotsAllocated++;
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Line.Slots.push_back(FI);
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++Line.Index;
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return FI;
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}
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// Sort all registers to spill in descendent order. In the
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// FixupSCSExtendSlotSize mode it will minimize the total frame size.
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// In non FixupSCSExtendSlotSize mode we can skip this step.
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void sortRegisters(SmallVectorImpl<Register> &Regs) {
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if (!FixupSCSExtendSlotSize)
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return;
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llvm::sort(Regs.begin(), Regs.end(), [&](Register &A, Register &B) {
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return getRegisterSize(TRI, A) > getRegisterSize(TRI, B);
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});
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}
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};
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// Describes the state of the current processing statepoint instruction.
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class StatepointState {
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private:
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// statepoint instruction.
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MachineInstr &MI;
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MachineFunction &MF;
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const TargetRegisterInfo &TRI;
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const TargetInstrInfo &TII;
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MachineFrameInfo &MFI;
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// Mask with callee saved registers.
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const uint32_t *Mask;
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// Cache of frame indexes used on previous instruction processing.
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FrameIndexesCache &CacheFI;
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// Operands with physical registers requiring spilling.
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SmallVector<unsigned, 8> OpsToSpill;
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// Set of register to spill.
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SmallVector<Register, 8> RegsToSpill;
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// Map Register to Frame Slot index.
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DenseMap<Register, int> RegToSlotIdx;
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public:
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StatepointState(MachineInstr &MI, const uint32_t *Mask,
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FrameIndexesCache &CacheFI)
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: MI(MI), MF(*MI.getMF()), TRI(*MF.getSubtarget().getRegisterInfo()),
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TII(*MF.getSubtarget().getInstrInfo()), MFI(MF.getFrameInfo()),
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Mask(Mask), CacheFI(CacheFI) {}
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// Return true if register is callee saved.
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bool isCalleeSaved(Register Reg) { return (Mask[Reg / 32] >> Reg % 32) & 1; }
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// Iterates over statepoint meta args to find caller saver registers.
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// Also cache the size of found registers.
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// Returns true if caller save registers found.
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bool findRegistersToSpill() {
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SmallSet<Register, 8> VisitedRegs;
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for (unsigned Idx = StatepointOpers(&MI).getVarIdx(),
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EndIdx = MI.getNumOperands();
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Idx < EndIdx; ++Idx) {
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MachineOperand &MO = MI.getOperand(Idx);
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if (!MO.isReg() || MO.isImplicit())
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continue;
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Register Reg = MO.getReg();
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assert(Reg.isPhysical() && "Only physical regs are expected");
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if (isCalleeSaved(Reg))
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continue;
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if (VisitedRegs.insert(Reg).second)
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RegsToSpill.push_back(Reg);
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OpsToSpill.push_back(Idx);
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}
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CacheFI.sortRegisters(RegsToSpill);
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return !RegsToSpill.empty();
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}
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// Spill all caller saved registers right before statepoint instruction.
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// Remember frame index where register is spilled.
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void spillRegisters() {
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for (Register Reg : RegsToSpill) {
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int FI = CacheFI.getFrameIndex(Reg);
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const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(*MI.getParent(), MI, Reg, true /*is_Kill*/, FI,
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RC, &TRI);
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NumSpilledRegisters++;
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RegToSlotIdx[Reg] = FI;
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}
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}
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// Re-write statepoint machine instruction to replace caller saved operands
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// with indirect memory location (frame index).
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void rewriteStatepoint() {
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MachineInstr *NewMI =
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MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
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MachineInstrBuilder MIB(MF, NewMI);
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// Add End marker.
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OpsToSpill.push_back(MI.getNumOperands());
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unsigned CurOpIdx = 0;
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for (unsigned I = 0; I < MI.getNumOperands(); ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (I == OpsToSpill[CurOpIdx]) {
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int FI = RegToSlotIdx[MO.getReg()];
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MIB.addImm(StackMaps::IndirectMemRefOp);
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MIB.addImm(getRegisterSize(TRI, MO.getReg()));
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assert(MO.isReg() && "Should be register");
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assert(MO.getReg().isPhysical() && "Should be physical register");
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MIB.addFrameIndex(FI);
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MIB.addImm(0);
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++CurOpIdx;
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} else
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MIB.add(MO);
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}
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assert(CurOpIdx == (OpsToSpill.size() - 1) && "Not all operands processed");
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// Add mem operands.
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NewMI->setMemRefs(MF, MI.memoperands());
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for (auto It : RegToSlotIdx) {
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int FrameIndex = It.second;
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auto PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIndex);
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auto *MMO = MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
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getRegisterSize(TRI, It.first),
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MFI.getObjectAlign(FrameIndex));
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NewMI->addMemOperand(MF, MMO);
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}
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// Insert new statepoint and erase old one.
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MI.getParent()->insert(MI, NewMI);
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MI.eraseFromParent();
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}
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};
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class StatepointProcessor {
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private:
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MachineFunction &MF;
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const TargetRegisterInfo &TRI;
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FrameIndexesCache CacheFI;
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public:
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StatepointProcessor(MachineFunction &MF)
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: MF(MF), TRI(*MF.getSubtarget().getRegisterInfo()),
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CacheFI(MF.getFrameInfo(), TRI) {}
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bool process(MachineInstr &MI) {
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StatepointOpers SO(&MI);
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uint64_t Flags = SO.getFlags();
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// Do nothing for LiveIn, it supports all registers.
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if (Flags & (uint64_t)StatepointFlags::DeoptLiveIn)
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return false;
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CallingConv::ID CC = SO.getCallingConv();
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const uint32_t *Mask = TRI.getCallPreservedMask(MF, CC);
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CacheFI.reset();
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StatepointState SS(MI, Mask, CacheFI);
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if (!SS.findRegistersToSpill())
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return false;
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SS.spillRegisters();
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SS.rewriteStatepoint();
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return true;
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}
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};
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} // namespace
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bool FixupStatepointCallerSaved::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const Function &F = MF.getFunction();
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if (!F.hasGC())
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return false;
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SmallVector<MachineInstr *, 16> Statepoints;
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for (MachineBasicBlock &BB : MF)
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for (MachineInstr &I : BB)
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if (I.getOpcode() == TargetOpcode::STATEPOINT)
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Statepoints.push_back(&I);
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if (Statepoints.empty())
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return false;
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bool Changed = false;
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StatepointProcessor SPP(MF);
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for (MachineInstr *I : Statepoints)
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Changed |= SPP.process(*I);
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return Changed;
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}
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