forked from OSchip/llvm-project
110 lines
4.1 KiB
TableGen
110 lines
4.1 KiB
TableGen
//===- Nios2InstrInfo.td - Target Description for Nios2 ------*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Nios2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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include "Nios2InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Nios2 Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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def simm16 : Operand<i32> {
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let DecoderMethod= "DecodeSimm16";
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}
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
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// Custom return SDNode
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def Nios2Ret : SDNode<"Nios2ISD::Ret", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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// Arithmetic and logical instructions with 2 registers and 16-bit immediate
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// value.
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multiclass ArithLogicRegImm16<bits<6> op, string mnemonic, SDNode opNode,
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Operand immOp, PatLeaf immType>:
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CommonInstr_I_F2I16<op, (outs CPURegs:$rB),
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(ins CPURegs:$rA, immOp:$imm),
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!strconcat(mnemonic, "\t$rB, $rA, $imm"),
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[(set CPURegs:$rB,
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(opNode CPURegs:$rA, immType:$imm))],
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IIAlu>;
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// Arithmetic and logical instructions with 3 register operands.
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// Defines R1 and R2 instruction at the same time.
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multiclass ArithLogicReg<bits<6> opx, string mnemonic,
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SDNode opNode>:
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CommonInstr_R_F3X6<opx, (outs CPURegs:$rC),
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(ins CPURegs:$rA, CPURegs:$rB),
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!strconcat(mnemonic, "\t$rC, $rA, $rB"),
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[(set CPURegs:$rC, (opNode CPURegs:$rA, CPURegs:$rB))],
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IIAlu>;
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multiclass Return<bits<6> opx, dag outs, dag ins, string mnemonic> {
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let rB = 0, rC = 0,
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isReturn = 1,
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isCodeGenOnly = 1,
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hasCtrlDep = 1,
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hasExtraSrcRegAllocReq = 1 in {
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defm NAME# : CommonInstr_R_F3X6<opx, outs, ins, mnemonic, [], IIBranch>;
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}
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}
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//===----------------------------------------------------------------------===//
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// Nios2 Instructions
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//===----------------------------------------------------------------------===//
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/// Arithmetic instructions operating on registers.
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let isCommutable = 1 ,
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isReMaterializable = 1 in {
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defm ADD : ArithLogicReg<0x31, "add", add>;
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defm AND : ArithLogicReg<0x0e, "and", and>;
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defm OR : ArithLogicReg<0x16, "or", or>;
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defm XOR : ArithLogicReg<0x1e, "xor", xor>;
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defm MUL : ArithLogicReg<0x27, "mul", mul>;
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}
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let isReMaterializable = 1 in {
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defm SUB : ArithLogicReg<0x39, "sub", sub>;
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}
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defm DIVU : ArithLogicReg<0x24, "divu", udiv>;
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defm DIV : ArithLogicReg<0x25, "div", sdiv>;
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defm SLL : ArithLogicReg<0x13, "sll", shl>;
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defm SRL : ArithLogicReg<0x1b, "srl", srl>;
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defm SRA : ArithLogicReg<0x3b, "sra", sra>;
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/// Arithmetic Instructions (ALU Immediate)
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defm ADDI : ArithLogicRegImm16<0x04, "addi", add, simm16, immSExt16>;
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// Returns:
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defm RET : Return<0x05, (outs), (ins CPURegs:$rA), "ret">;
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//===----------------------------------------------------------------------===//
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// Pseudo instructions
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//===----------------------------------------------------------------------===//
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// Return RA.
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let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
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def RetRA : Nios2Pseudo<(outs), (ins), "", [(Nios2Ret)]>;
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