..
AsmParser
[Hexagon] Modifying r262258 to only be in effect in the hand assembler path, not the integrated assembler.
2016-03-01 21:37:41 +00:00
Disassembler
[Hexagon] Adding missing break in switch statement. Extra operands would have been appended to the end.
2016-03-16 20:00:38 +00:00
MCTargetDesc
[Hexagon] Add handling fixups and instruction relaxation
2016-03-21 20:27:17 +00:00
TargetInfo
Remove autoconf support
2016-01-26 21:29:08 +00:00
BitTracker.cpp
[Hexagon] Fix compilation error with GCC 6
2016-02-18 16:10:27 +00:00
BitTracker.h
-Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11
2015-08-01 05:31:27 +00:00
CMakeLists.txt
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
Hexagon.h
[Hexagon] Improve lowering of instructions to the MC layer
2015-12-02 23:08:29 +00:00
Hexagon.td
[TableGen] Modify the AsmMatcherEmitter to only apply the table growth from r252440 to the Hexagon target.
2015-12-31 08:18:23 +00:00
HexagonAsmPrinter.cpp
Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"
2016-02-22 20:49:58 +00:00
HexagonAsmPrinter.h
[Hexagon] Preprocess mapped instructions before lowering to MC
2015-12-15 17:05:45 +00:00
HexagonBitSimplify.cpp
[Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfword
2016-01-14 21:59:22 +00:00
HexagonBitTracker.cpp
CodeGen: TII: Take MachineInstr& in predicate API, NFC
2016-02-23 02:46:52 +00:00
HexagonBitTracker.h
[Hexagon] Move BitTracker into the llvm namespace and remove redundant qualifications
2015-07-13 20:38:16 +00:00
HexagonBlockRanges.cpp
Fix Windows buildbot breakage.
2016-02-12 23:51:06 +00:00
HexagonBlockRanges.h
[Hexagon] Optimize stack slot spills
2016-02-12 22:53:35 +00:00
HexagonCFGOptimizer.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonCallingConv.td
…
HexagonCommonGEP.cpp
Introduce analysis pass to compute PostDominators in the new pass manager. NFC
2016-02-25 17:54:07 +00:00
HexagonCopyToCombine.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonEarlyIfConv.cpp
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
2016-02-27 17:05:33 +00:00
HexagonExpandCondsets.cpp
CodeGen: Take MachineInstr& in SlotIndexes and LiveIntervals, NFC
2016-02-27 06:40:41 +00:00
HexagonFixupHwLoops.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonFrameLowering.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonFrameLowering.h
Change eliminateCallFramePseudoInstr() to return an iterator
2016-03-31 18:33:38 +00:00
HexagonGenExtract.cpp
Hexagon: Remove implicit ilist iterator conversions, NFC
2015-10-20 00:46:39 +00:00
HexagonGenInsert.cpp
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
2016-02-27 17:05:33 +00:00
HexagonGenMux.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonGenPredicate.cpp
WIP: CodeGen: Use MachineInstr& in MachineInstrBundle.h, NFC
2016-02-27 17:05:33 +00:00
HexagonHardwareLoops.cpp
Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"
2016-02-22 20:49:58 +00:00
HexagonISelDAGToDAG.cpp
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
HexagonISelLowering.cpp
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
HexagonISelLowering.h
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
HexagonInstrAlias.td
[Hexagon] Adding instruction aliases and tests.
2015-11-10 01:58:26 +00:00
HexagonInstrEnc.td
[Hexagon] Adding skeleton of HVX extension instructions.
2015-10-17 01:33:04 +00:00
HexagonInstrFormats.td
[Hexagon] Remove the remnants of isConstExtProfitable
2015-10-20 19:04:53 +00:00
HexagonInstrFormatsV4.td
[Hexagon] Update instruction formats
2015-11-23 14:09:26 +00:00
HexagonInstrFormatsV60.td
[Hexagon] Update instruction formats
2015-11-23 14:09:26 +00:00
HexagonInstrInfo.cpp
[Hexagon] Generate PIC-specific versions of save/restore routines
2016-03-24 19:18:48 +00:00
HexagonInstrInfo.h
CodeGen: TII: Take MachineInstr& in predicate API, NFC
2016-02-23 02:46:52 +00:00
HexagonInstrInfo.td
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
2016-02-16 20:38:17 +00:00
HexagonInstrInfoV3.td
[Hexagon] Add support for run-time stack overflow checking
2016-03-24 20:20:07 +00:00
HexagonInstrInfoV4.td
[Hexagon] Add support for run-time stack overflow checking
2016-03-24 20:20:07 +00:00
HexagonInstrInfoV5.td
[Hexagon] Treat transfers of FP immediates are pseudo instructions
2015-11-25 21:40:03 +00:00
HexagonInstrInfoV60.td
[Hexagon] Improve handling of unaligned vector loads and stores
2016-03-28 15:43:03 +00:00
HexagonInstrInfoVector.td
[Hexagon] Hexagon V60 HVX intrinsic defintions
2015-11-26 16:54:33 +00:00
HexagonIntrinsics.td
[Hexagon] Eliminate pseudo instructions for circ/brev loads and stores
2016-02-12 17:01:51 +00:00
HexagonIntrinsicsDerived.td
…
HexagonIntrinsicsV3.td
…
HexagonIntrinsicsV4.td
…
HexagonIntrinsicsV5.td
…
HexagonIntrinsicsV60.td
[Hexagon] Hexagon V60 HVX intrinsic defintions
2015-11-26 16:54:33 +00:00
HexagonIsetDx.td
[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
2015-06-05 16:00:11 +00:00
HexagonMCInstLower.cpp
[Hexagon] Using MustExtend flag on expression instead of passing around bools.
2016-02-29 18:39:51 +00:00
HexagonMachineFunctionInfo.cpp
…
HexagonMachineFunctionInfo.h
[Hexagon] Speed up frame lowering when no optimizations are enabled
2016-03-28 14:42:03 +00:00
HexagonMachineScheduler.cpp
CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
2016-02-27 19:09:00 +00:00
HexagonMachineScheduler.h
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
2015-06-23 09:49:53 +00:00
HexagonNewValueJump.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonOperands.td
[Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding.
2016-02-16 20:38:17 +00:00
HexagonOptimizeSZextends.cpp
Hexagon: Remove implicit ilist iterator conversions, NFC
2015-10-20 00:46:39 +00:00
HexagonPeephole.cpp
CodeGen: TII: Take MachineInstr& in predicate API, NFC
2016-02-23 02:46:52 +00:00
HexagonRDF.cpp
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
HexagonRDF.h
[Hexagon] Implement RDF-based post-RA optimizations
2016-01-12 19:09:01 +00:00
HexagonRDFOpt.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonRegisterInfo.cpp
[Hexagon] Fix reserving emergency spill slots for register scavenger
2016-03-21 19:57:08 +00:00
HexagonRegisterInfo.h
[Hexagon] Fix reserving emergency spill slots for register scavenger
2016-03-21 19:57:08 +00:00
HexagonRegisterInfo.td
[Hexagon] Mark HVX registers as volatile
2016-02-12 22:26:44 +00:00
HexagonSchedule.td
[Hexagon] Update instruction formats
2015-11-23 14:09:26 +00:00
HexagonScheduleV4.td
TableGen: Check scheduling models for completeness
2016-03-01 20:03:21 +00:00
HexagonScheduleV55.td
TableGen: Check scheduling models for completeness
2016-03-01 20:03:21 +00:00
HexagonScheduleV60.td
TableGen: Check scheduling models for completeness
2016-03-01 20:03:21 +00:00
HexagonSelectCCInfo.td
…
HexagonSelectionDAGInfo.cpp
[Hexagon] Make memcpy lowering thread-safe
2015-12-16 17:29:37 +00:00
HexagonSelectionDAGInfo.h
Rename TargetSelectionDAGInfo into SelectionDAGTargetInfo and move it to CodeGen/
2016-01-27 16:32:26 +00:00
HexagonSplitConst32AndConst64.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonSplitDouble.cpp
[Hexagon] Split double registers
2015-10-16 20:38:54 +00:00
HexagonStoreWidening.cpp
[Hexagon] Merge adjacent stores
2015-10-16 19:43:56 +00:00
HexagonSubtarget.cpp
[Hexagon] Subtarget features/default CPU corrections
2015-12-14 15:03:54 +00:00
HexagonSubtarget.h
[Hexagon] Subtarget features/default CPU corrections
2015-12-14 15:03:54 +00:00
HexagonSystemInst.td
[Hexagon] Add system instructions for cache manipulation
2016-01-06 14:22:22 +00:00
HexagonTargetMachine.cpp
[Hexagon] Remove HexagonExpandPredSpillCode pass
2016-02-12 17:09:58 +00:00
HexagonTargetMachine.h
[Hexagon] Add PIC support
2015-12-18 20:19:30 +00:00
HexagonTargetObjectFile.cpp
GlobalValue: use getValueType() instead of getType()->getPointerElementType().
2016-01-16 20:30:46 +00:00
HexagonTargetObjectFile.h
Move alignment from MCSectionData to MCSection.
2015-05-21 19:20:38 +00:00
HexagonTargetStreamer.h
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
2015-06-23 09:49:53 +00:00
HexagonTargetTransformInfo.cpp
[Hexagon] Edit a comment. NFC
2015-08-05 21:08:26 +00:00
HexagonTargetTransformInfo.h
constify the Function parameter to the TTI creation callback and
2015-09-16 23:38:13 +00:00
HexagonVLIWPacketizer.cpp
Add MachineFunctionProperty checks for AllVRegsAllocated for target passes
2016-04-04 17:09:25 +00:00
HexagonVLIWPacketizer.h
CodeGen: Update DFAPacketizer API to take MachineInstr&, NFC
2016-02-27 19:09:00 +00:00
LLVMBuild.txt
[Hexagon] Adding LLVMBuild.txt reference to HexagonAsmParser.
2015-11-09 04:31:02 +00:00
RDFCopy.cpp
[RDF] Improvements to copy propagation
2016-01-18 20:43:57 +00:00
RDFCopy.h
[RDF] Improvements to copy propagation
2016-01-18 20:43:57 +00:00
RDFDeadCode.cpp
[RDF] Improve compile-time performance of dead code elimination
2016-01-18 20:42:47 +00:00
RDFDeadCode.h
[RDF] Improve compile-time performance of dead code elimination
2016-01-18 20:42:47 +00:00
RDFGraph.cpp
CodeGen: TII: Take MachineInstr& in predicate API, NFC
2016-02-23 02:46:52 +00:00
RDFGraph.h
[RDF] Allow unlinking ref nodes from data-flow chains only
2016-01-18 20:41:34 +00:00
RDFLiveness.cpp
RDF: Implement register liveness analysis
2016-01-12 15:56:33 +00:00
RDFLiveness.h
RDF: Implement register liveness analysis
2016-01-12 15:56:33 +00:00