forked from OSchip/llvm-project
203 lines
7.0 KiB
C++
203 lines
7.0 KiB
C++
//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the AArch64 specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
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#include "AArch64FrameLowering.h"
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#include "AArch64GISelAccessor.h"
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#include "AArch64ISelLowering.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64SelectionDAGInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "AArch64GenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class Triple;
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class AArch64Subtarget : public AArch64GenSubtargetInfo {
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protected:
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enum ARMProcFamilyEnum {
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Others,
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CortexA35,
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CortexA53,
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CortexA57,
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Cyclone,
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ExynosM1,
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Kryo
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};
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/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
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ARMProcFamilyEnum ARMProcFamily;
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bool HasV8_1aOps;
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bool HasV8_2aOps;
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bool HasFPARMv8;
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bool HasNEON;
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bool HasCrypto;
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bool HasCRC;
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bool HasPerfMon;
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bool HasFullFP16;
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bool HasSPE;
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// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
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bool HasZeroCycleRegMove;
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// HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
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bool HasZeroCycleZeroing;
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// StrictAlign - Disallow unaligned memory accesses.
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bool StrictAlign;
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// ReserveX18 - X18 is not available as a general purpose register.
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bool ReserveX18;
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bool IsLittle;
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/// CPUString - String name of used CPU.
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std::string CPUString;
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/// TargetTriple - What processor and OS we're targeting.
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Triple TargetTriple;
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AArch64FrameLowering FrameLowering;
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AArch64InstrInfo InstrInfo;
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AArch64SelectionDAGInfo TSInfo;
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AArch64TargetLowering TLInfo;
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/// Gather the accessor points to GlobalISel-related APIs.
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/// This is used to avoid ifndefs spreading around while GISel is
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/// an optional library.
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std::unique_ptr<AArch64GISelAccessor> GISelAccessor;
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private:
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/// initializeSubtargetDependencies - Initializes using CPUString and the
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/// passed in feature string so that we can use initializer lists for
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/// subtarget initialization.
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AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
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public:
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/// This constructor initializes the data members to match that
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/// of the specified triple.
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AArch64Subtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM,
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bool LittleEndian);
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/// This object will take onwership of \p GISelAccessor.
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void setGISelAccessor(AArch64GISelAccessor &GISelAccessor) {
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this->GISelAccessor.reset(&GISelAccessor);
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}
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const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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const AArch64FrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const AArch64TargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const AArch64RegisterInfo *getRegisterInfo() const override {
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return &getInstrInfo()->getRegisterInfo();
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}
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const CallLowering *getCallLowering() const override;
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const RegisterBankInfo *getRegBankInfo() const override;
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const Triple &getTargetTriple() const { return TargetTriple; }
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bool enableMachineScheduler() const override { return true; }
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bool enablePostRAScheduler() const override {
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return isGeneric() || isCortexA53() || isCortexA57() || isKryo();
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}
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bool hasV8_1aOps() const { return HasV8_1aOps; }
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bool hasV8_2aOps() const { return HasV8_2aOps; }
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bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
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bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
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bool requiresStrictAlign() const { return StrictAlign; }
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bool isX18Reserved() const { return ReserveX18; }
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bool hasFPARMv8() const { return HasFPARMv8; }
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bool hasNEON() const { return HasNEON; }
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bool hasCrypto() const { return HasCrypto; }
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bool hasCRC() const { return HasCRC; }
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/// CPU has TBI (top byte of addresses is ignored during HW address
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/// translation) and OS enables it.
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bool supportsAddressTopByteIgnored() const;
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bool hasPerfMon() const { return HasPerfMon; }
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bool hasFullFP16() const { return HasFullFP16; }
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bool hasSPE() const { return HasSPE; }
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bool isLittleEndian() const { return IsLittle; }
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bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
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bool isTargetIOS() const { return TargetTriple.isiOS(); }
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bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
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bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
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bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
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bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
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bool isGeneric() const { return CPUString == "generic"; }
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bool isCyclone() const { return CPUString == "cyclone"; }
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bool isCortexA57() const { return CPUString == "cortex-a57"; }
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bool isCortexA53() const { return CPUString == "cortex-a53"; }
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bool isExynosM1() const { return CPUString == "exynos-m1"; }
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bool isKryo() const { return CPUString == "kryo"; }
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bool useAA() const override { return isCortexA53(); }
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/// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
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/// that still makes it profitable to inline the call.
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unsigned getMaxInlineSizeThreshold() const { return 64; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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/// ClassifyGlobalReference - Find the target operand flags that describe
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/// how a global value should be referenced for the current subtarget.
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unsigned char ClassifyGlobalReference(const GlobalValue *GV,
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const TargetMachine &TM) const;
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/// This function returns the name of a function which has an interface
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/// like the non-standard bzero function, if such a function exists on
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/// the current subtarget and it is considered prefereable over
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/// memset with zero passed as the second argument. Otherwise it
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/// returns null.
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const char *getBZeroEntry() const;
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void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
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MachineInstr *end,
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unsigned NumRegionInstrs) const override;
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bool enableEarlyIfConversion() const override;
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std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
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};
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} // End llvm namespace
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#endif
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