llvm-project/llvm/test/MC
Peter Collingbourne a67161fffa MC: Don't align COFF section contents.
Aligning section contents is not required, but only
recommended, by the specification. Microsoft's documentation says
(https://docs.microsoft.com/en-us/windows/desktop/debug/pe-format#section-table-section-headers):
"For object files, the value should be aligned on a 4-byte boundary
for best performance."

However, according to my measurements, aligning section contents has
a neutral to negative effect on performance.

I measured the median run time of 100 links of Chromium's
base_unittests on Linux with lld-link and on Windows with link.exe with
both aligned and unaligned sections. On Linux I didn't see a measurable
performance difference, and on Windows the link was slightly faster
with unaligned sections (presumably because on Windows the bottleneck
is I/O).

Also, the sections created by cl.exe are unaligned, so we should expect
tools to broadly accept unaligned sections.

Differential Revision: https://reviews.llvm.org/D51149

llvm-svn: 340514
2018-08-23 05:39:36 +00:00
..
AArch64 [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
AMDGPU [AMDGPU] New tbuffer intrinsics 2018-08-21 11:06:05 +00:00
ARM [ARM/AArch64] Support FP16 +fp16fml instructions 2018-08-17 11:29:49 +00:00
AVR [AVR] Implement some missing code paths 2017-12-11 11:01:27 +00:00
AsmParser [AsmParser] Fix preserve-comments-crlf.s on FreeBSD 2018-07-26 06:07:03 +00:00
BPF bpf: New disassembler testcases for 32-bit subregister support 2018-02-23 23:49:35 +00:00
COFF MC: Don't align COFF section contents. 2018-08-23 05:39:36 +00:00
Disassembler [WebAssembly] v128.const 2018-08-21 21:03:18 +00:00
ELF MC: Teach the COFF object writer to write address-significance tables. 2018-08-22 23:58:16 +00:00
Hexagon Check for tied operands 2018-08-13 14:01:25 +00:00
Lanai
MachO [MC] Error on a .zerofill directive in a non-virtual section 2018-07-02 17:29:43 +00:00
Mips [mips] Replace custom parsing logic for data directives by the `addAliasForDirective` 2018-07-25 07:07:43 +00:00
PowerPC Complete the SPE instruction set patterns 2018-07-18 04:24:57 +00:00
RISCV [RISC-V] Fixed alias for addi x2, x2, 0 2018-08-09 20:51:53 +00:00
Sparc [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SystemZ [SystemZ, AsmParser] Enable the mnemonic spell corrector. 2017-07-18 09:17:00 +00:00
WebAssembly [WebAssembly] v128.const 2018-08-21 21:03:18 +00:00
X86 [MC][X86] Enhance X86 Register expression handling to more closely match GCC. 2018-08-16 16:31:14 +00:00