forked from OSchip/llvm-project
20 lines
665 B
LLVM
20 lines
665 B
LLVM
; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i64 @llvm.amdgcn.dispatch.id() #1
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; GCN-LABEL: {{^}}dispatch_id:
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; GCN: .amd_kernel_code_t
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; GCN: enable_sgpr_dispatch_id = 1
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; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
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; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], s7
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
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define amdgpu_kernel void @dispatch_id(i64 addrspace(1)* %out) #0 {
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%tmp0 = call i64 @llvm.amdgcn.dispatch.id()
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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