forked from OSchip/llvm-project
164 lines
5.8 KiB
LLVM
164 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
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define i32 @s_add_co_select_user() {
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; GFX7-LABEL: s_add_co_select_user:
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; GFX7: ; %bb.0: ; %bb
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; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX7-NEXT: s_mov_b64 s[4:5], 0
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; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
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; GFX7-NEXT: s_or_b32 s4, s4, s5
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; GFX7-NEXT: s_cmp_lg_u32 s4, 0
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; GFX7-NEXT: s_addc_u32 s4, s6, 0
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; GFX7-NEXT: v_mov_b32_e32 v1, s4
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; GFX7-NEXT: s_cselect_b64 vcc, 1, 0
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; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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; GFX7-NEXT: v_cmp_gt_u32_e64 vcc, s6, 31
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; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GFX7-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-LABEL: s_add_co_select_user:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: s_mov_b64 s[4:5], 0
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; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
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; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
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; GFX9-NEXT: s_addc_u32 s4, s6, 0
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; GFX9-NEXT: s_cselect_b64 vcc, 1, 0
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; GFX9-NEXT: v_mov_b32_e32 v1, s4
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; GFX9-NEXT: s_cmp_gt_u32 s6, 31
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; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
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; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
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; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: s_add_co_select_user:
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; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX10-NEXT: s_mov_b64 s[4:5], 0
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; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_add_co_u32_e64 v0, s5, s4, s4
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; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0
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; GFX10-NEXT: s_addc_u32 s5, s4, 0
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; GFX10-NEXT: s_cselect_b32 s6, 1, 0
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; GFX10-NEXT: s_cmp_gt_u32 s4, 31
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; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6
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; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
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; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = load volatile i32, i32 addrspace(4)* null, align 8
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%i1 = add i32 %i, %i
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%i2 = icmp ult i32 %i1, %i
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%i3 = zext i1 %i2 to i32
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%i4 = add nuw nsw i32 %i3, 0
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%i5 = add i32 %i4, %i
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%i6 = icmp ult i32 %i5, %i4
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%i7 = select i1 %i6, i32 %i5, i32 0
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%i8 = icmp ugt i32 %i, 31
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%i9 = select i1 %i8, i32 %i1, i32 %i7
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ret i32 %i9
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}
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define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
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; GFX7-LABEL: s_add_co_br_user:
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; GFX7: ; %bb.0: ; %bb
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; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: s_add_i32 s1, s0, s0
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; GFX7-NEXT: v_mov_b32_e32 v0, s0
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; GFX7-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0
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; GFX7-NEXT: s_or_b32 s1, vcc_lo, vcc_hi
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; GFX7-NEXT: s_cmp_lg_u32 s1, 0
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; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX7-NEXT: s_addc_u32 s0, s0, 0
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; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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; GFX7-NEXT: s_and_b64 vcc, exec, vcc
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; GFX7-NEXT: s_cbranch_vccnz BB1_2
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; GFX7-NEXT: ; %bb.1: ; %bb0
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: v_mov_b32_e32 v2, 9
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; GFX7-NEXT: v_mov_b32_e32 v1, 0
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; GFX7-NEXT: flat_store_dword v[0:1], v2
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; GFX7-NEXT: BB1_2: ; %bb1
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; GFX7-NEXT: v_mov_b32_e32 v0, 0
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; GFX7-NEXT: v_mov_b32_e32 v2, 10
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; GFX7-NEXT: v_mov_b32_e32 v1, 0
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; GFX7-NEXT: flat_store_dword v[0:1], v2
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; GFX7-NEXT: s_endpgm
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;
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; GFX9-LABEL: s_add_co_br_user:
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; GFX9: ; %bb.0: ; %bb
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; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_add_i32 s1, s0, s0
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; GFX9-NEXT: v_mov_b32_e32 v0, s0
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; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0
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; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
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; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX9-NEXT: s_addc_u32 s0, s0, 0
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; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
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; GFX9-NEXT: s_and_b64 vcc, exec, vcc
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; GFX9-NEXT: s_cbranch_vccnz BB1_2
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; GFX9-NEXT: ; %bb.1: ; %bb0
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v2, 9
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: BB1_2: ; %bb1
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v2, 10
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; GFX9-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-NEXT: global_store_dword v[0:1], v2, off
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_add_co_br_user:
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; GFX10: ; %bb.0: ; %bb
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; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_add_i32 s1, s0, s0
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; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0
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; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
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; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
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; GFX10-NEXT: s_addc_u32 s0, s0, 0
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; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
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; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
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; GFX10-NEXT: s_cbranch_vccnz BB1_2
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; GFX10-NEXT: ; %bb.1: ; %bb0
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: v_mov_b32_e32 v2, 9
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: global_store_dword v[0:1], v2, off
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; GFX10-NEXT: BB1_2: ; %bb1
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: v_mov_b32_e32 v2, 10
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; GFX10-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-NEXT: global_store_dword v[0:1], v2, off
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; GFX10-NEXT: s_endpgm
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bb:
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%i1 = add i32 %i, %i
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%i2 = icmp ult i32 %i1, %i
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%i3 = zext i1 %i2 to i32
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%i4 = add nuw nsw i32 %i3, 0
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%i5 = add i32 %i4, %i
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%i6 = icmp ult i32 %i5, %i4
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%i7 = select i1 %i6, i32 %i5, i32 0
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br i1 %i6, label %bb0, label %bb1
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bb0:
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store volatile i32 9, i32 addrspace(1)* null
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br label %bb1
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bb1:
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store volatile i32 10, i32 addrspace(1)* null
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ret void
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}
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