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llvm-project/llvm/lib/Target/VE
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Simon Moll 351c10cc72 [VE] Add +vpu attribute 
`+vpu` controls whether VEISelLowering adds any vregs.  This defaults to
`-vpu` to have scalar code generation out of the box.  We bring up
vector isel under the `+vpu` flag. Once vector isel is stable we switch
to `+vpu` and advertise vregs and vops in TTI.

Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D90465
 		2020-11-04 12:42:00 +01:00
..
AsmParser [VE] Add vector mask operation instructions 2020-10-29 08:42:41 +09:00
Disassembler [VE] Fix initializer visibility 2020-10-19 22:54:41 +01:00
MCTargetDesc [VE] Fix initializer visibility 2020-10-19 22:54:41 +01:00
TargetInfo [VE] Fix initializer visibility 2020-10-19 22:54:41 +01:00
CMakeLists.txt [VE] Support a basic disassembler for Aurora VE target 2020-06-03 13:48:42 +02:00
LLVMBuild.txt [VE] Support a basic disassembler for Aurora VE target 2020-06-03 13:48:42 +02:00
VE.h [VE] Support convert instructions in MC layer 2020-06-10 12:22:33 +02:00
VE.td [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VEAsmPrinter.cpp [VE] Fix initializer visibility 2020-10-19 22:54:41 +01:00
VECallingConv.td [VE] Support f128 2020-08-17 17:26:52 +09:00
VEFrameLowering.cpp [VE] Dynamic stack allocation 2020-05-27 10:11:06 +02:00
VEFrameLowering.h [VE] Dynamic stack allocation 2020-05-27 10:11:06 +02:00
VEISelDAGToDAG.cpp [VE] Support register and frame-index pair correctly 2020-10-05 18:36:53 +09:00
VEISelLowering.cpp [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VEISelLowering.h [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VEInstrFormats.td [VE] Add VBRD/VMV instructions 2020-10-19 18:33:54 +09:00
VEInstrInfo.cpp [VE] Support f128 2020-08-17 17:26:52 +09:00
VEInstrInfo.h [VE] Add vector load/store instructions 2020-10-15 09:26:55 +09:00
VEInstrInfo.td [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
VEInstrVec.td [VE] Add vector control instructions 2020-10-29 19:24:31 +09:00
VEMCInstLower.cpp [VE] Support TargetBlockAddress 2020-10-01 00:48:21 +09:00
VEMachineFunctionInfo.cpp
…
VEMachineFunctionInfo.h
…
VERegisterInfo.cpp [VE] Support f128 2020-08-17 17:26:52 +09:00
VERegisterInfo.h [VE] Adapt aa26dd9858 and 2481f26ac3 2020-04-07 15:45:19 -07:00
VERegisterInfo.td [VE] Support register aliases in llvm-mc 2020-10-29 23:28:32 +09:00
VESubtarget.cpp [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VESubtarget.h [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00
VETargetMachine.cpp [VE] Support atomic load 2020-10-26 18:02:45 +09:00
VETargetMachine.h [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
VETargetTransformInfo.h [VE] Add +vpu attribute 2020-11-04 12:42:00 +01:00