forked from OSchip/llvm-project
180 lines
4.3 KiB
YAML
180 lines
4.3 KiB
YAML
# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define i32 @test_cmp_i8(i8 %a, i8 %b) {
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%r = icmp ult i8 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_cmp_i16(i16 %a, i16 %b) {
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%r = icmp ult i16 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_cmp_i32(i32 %a, i32 %b) {
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%r = icmp ult i32 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_cmp_i64(i64 %a, i64 %b) {
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%r = icmp ult i64 %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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define i32 @test_cmp_p0(i32* %a, i32* %b) {
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%r = icmp ult i32* %a, %b
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%res = zext i1 %r to i32
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ret i32 %res
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}
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...
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---
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name: test_cmp_i8
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# CHECK-LABEL: name: test_cmp_i8
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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# CHECK: %0(s8) = COPY %dil
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# CHECK-NEXT: %1(s8) = COPY %sil
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# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s8), %1
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# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
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# CHECK-NEXT: %eax = COPY %3(s32)
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# CHECK-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s8) = COPY %dil
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%1(s8) = COPY %sil
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%2(s1) = G_ICMP intpred(ult), %0(s8), %1
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%3(s32) = G_ZEXT %2(s1)
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%eax = COPY %3(s32)
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RET 0, implicit %eax
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...
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---
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name: test_cmp_i16
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# CHECK-LABEL: name: test_cmp_i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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# CHECK: %0(s16) = COPY %di
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# CHECK-NEXT: %1(s16) = COPY %si
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# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s16), %1
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# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
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# CHECK-NEXT: %eax = COPY %3(s32)
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# CHECK-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s16) = COPY %di
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%1(s16) = COPY %si
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%2(s1) = G_ICMP intpred(ult), %0(s16), %1
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%3(s32) = G_ZEXT %2(s1)
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%eax = COPY %3(s32)
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RET 0, implicit %eax
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...
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---
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name: test_cmp_i32
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# CHECK-LABEL: name: test_cmp_i32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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# CHECK: %0(s32) = COPY %edi
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# CHECK-NEXT: %1(s32) = COPY %esi
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# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s32), %1
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# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
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# CHECK-NEXT: %eax = COPY %3(s32)
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# CHECK-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %edi, %esi
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%0(s32) = COPY %edi
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%1(s32) = COPY %esi
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%2(s1) = G_ICMP intpred(ult), %0(s32), %1
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%3(s32) = G_ZEXT %2(s1)
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%eax = COPY %3(s32)
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RET 0, implicit %eax
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...
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---
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name: test_cmp_i64
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# CHECK-LABEL: name: test_cmp_i64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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# CHECK: %0(s64) = COPY %rdi
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# CHECK-NEXT: %1(s64) = COPY %rsi
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# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(s64), %1
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# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
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# CHECK-NEXT: %eax = COPY %3(s32)
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# CHECK-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi, %rsi
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%0(s64) = COPY %rdi
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%1(s64) = COPY %rsi
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%2(s1) = G_ICMP intpred(ult), %0(s64), %1
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%3(s32) = G_ZEXT %2(s1)
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%eax = COPY %3(s32)
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RET 0, implicit %eax
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...
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---
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name: test_cmp_p0
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# CHECK-LABEL: name: test_cmp_p0
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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- { id: 3, class: _ }
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# CHECK: %0(p0) = COPY %rdi
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# CHECK-NEXT: %1(p0) = COPY %rsi
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# CHECK-NEXT: %2(s1) = G_ICMP intpred(ult), %0(p0), %1
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# CHECK-NEXT: %3(s32) = G_ZEXT %2(s1)
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# CHECK-NEXT: %eax = COPY %3(s32)
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# CHECK-NEXT: RET 0, implicit %eax
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body: |
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bb.1 (%ir-block.0):
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liveins: %rdi, %rsi
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%0(p0) = COPY %rdi
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%1(p0) = COPY %rsi
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%2(s1) = G_ICMP intpred(ult), %0(p0), %1
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%3(s32) = G_ZEXT %2(s1)
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%eax = COPY %3(s32)
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RET 0, implicit %eax
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...
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