llvm-project/llvm/test/CodeGen/Mips/Fast-ISel
Matt Arsenault c2e35a6f32 RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs
The 2nd loop calculates spill costs but reports free registers as cost
0 anyway, so there is little benefit from having a separate early
loop.

Surprisingly this is not NFC, as many register are marked regDisabled
so the first loop often picks up later registers unnecessarily instead
of the first one available in the allocation order...

Patch by Matthias Braun

llvm-svn: 356499
2019-03-19 19:01:34 +00:00
..
br1.ll
bricmpi1.ll
bswap1.ll
callabi.ll RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
check-disabled-mcpus.ll
constexpr-address.ll
div1.ll
double-arg.ll
fast-isel-softfloat-lower-args.ll
fastalloca.ll
fastcc-miss.ll
fpcmpa.ll
fpext.ll
fpintconv.ll
fptrunc.ll
icmpa.ll
icmpbr1.ll [Mips] Fix missing masking in fast-isel of br (PR40325) 2019-02-25 18:54:17 +00:00
icmpi1.ll
loadstore2.ll
loadstoreconv.ll
loadstrconst.ll
logopm.ll
memtest1.ll
mul1.ll
nullvoid.ll
overflt.ll
pr40325.ll RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
rem1.ll
retabi.ll
sel1.ll
shftopm.ll
shift.ll
simplestore.ll
simplestorefp1.ll
simplestorei.ll
stackloadstore.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00