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AsmParser
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[MC] De-capitalize another set of MCStreamer::Emit* functions
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2020-02-14 19:26:52 -08:00 |
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Disassembler
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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MCTargetDesc
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[NFC][RISCV] Fixing typo in comment.
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2020-02-05 11:30:11 -08:00 |
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TargetInfo
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CMake: Make most target symbols hidden by default
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2020-01-14 19:46:52 -08:00 |
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Utils
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[RISCV] Support ABI checking with per function target-features
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2020-01-22 08:12:28 -08:00 |
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CMakeLists.txt
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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LLVMBuild.txt
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCV.h
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCV.td
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVAsmPrinter.cpp
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[AsmPrinter][MCStreamer] De-capitalize EmitInstruction and EmitCFI*
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2020-02-13 22:08:55 -08:00 |
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RISCVCallLowering.cpp
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVCallLowering.h
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVCallingConv.td
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[RISCV] Rename FPRs and use Register arithmetic
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2019-09-27 15:49:10 +00:00 |
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RISCVExpandPseudoInsts.cpp
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[RISCV] Use addi rather than add x0
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2019-11-14 18:43:38 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVFrameLowering.h
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVISelDAGToDAG.cpp
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[SelectionDAG] Disallow indirect "i" constraint
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2019-12-29 16:50:42 -08:00 |
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RISCVISelLowering.cpp
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[LegalizeTypes][ARM][AArch64][PowerPC][RISCV][X86] Use BUILD_PAIR to return expanded integer results from ReplaceNodeResults instead of just returning two results.
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2020-02-08 09:52:31 -08:00 |
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RISCVISelLowering.h
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CodeGen: Use LLT instead of EVT in getRegisterByName
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2020-01-09 17:37:52 -05:00 |
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RISCVInstrFormats.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrFormatsC.td
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…
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RISCVInstrInfo.cpp
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[NFC] unsigned->Register in storeRegTo/loadRegFromStack
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2020-02-03 14:22:16 +01:00 |
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RISCVInstrInfo.h
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[NFC] unsigned->Register in storeRegTo/loadRegFromStack
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2020-02-03 14:22:16 +01:00 |
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RISCVInstrInfo.td
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[RISCV] Optimize seteq/setne pattern expansions for better code size
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2020-02-11 22:45:15 +08:00 |
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RISCVInstrInfoA.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoC.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoD.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoF.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstrInfoM.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVInstructionSelector.cpp
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVLegalizerInfo.cpp
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVLegalizerInfo.h
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVMCInstLower.cpp
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[RISCV] Add lowering of global TLS addresses
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2019-06-19 08:40:59 +00:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVMergeBaseOffset.cpp
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[RISCV] Convert registers from unsigned to Register
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2019-08-16 14:27:50 +00:00 |
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RISCVRegisterBankInfo.cpp
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVRegisterBankInfo.h
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVRegisterBanks.td
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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RISCVRegisterInfo.cpp
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[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler
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2020-02-15 09:14:04 +08:00 |
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RISCVRegisterInfo.h
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] Rename FPRs and use Register arithmetic
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2019-09-27 15:49:10 +00:00 |
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RISCVSchedRocket32.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVSchedRocket64.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVSchedule.td
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[RISCV] Scheduler description for the Rocket core
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2020-01-23 19:36:47 -06:00 |
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RISCVSubtarget.cpp
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Make llvm::StringRef to std::string conversions explicit.
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2020-01-28 23:25:25 +01:00 |
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RISCVSubtarget.h
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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RISCVSystemOperands.td
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[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references
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2019-07-05 12:16:40 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Check the target-abi module flag matches the option
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2020-01-21 07:32:12 -08:00 |
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RISCVTargetMachine.h
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[RISCV] Add subtargets initialized with target feature
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2019-12-17 09:34:01 -08:00 |
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RISCVTargetObjectFile.cpp
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Revert "Honor -fuse-init-array when os is not specified on x86"
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2019-12-17 07:36:59 -08:00 |
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RISCVTargetObjectFile.h
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…
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RISCVTargetTransformInfo.cpp
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Rename TTI::getIntImmCost for instructions and intrinsics
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2019-12-11 18:00:20 -08:00 |
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RISCVTargetTransformInfo.h
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Rename TTI::getIntImmCost for instructions and intrinsics
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2019-12-11 18:00:20 -08:00 |
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