Matt Arsenault 40bc9112c0 GlobalISel: Relax handling of G_ASSERT_* with source register classes ... The most common situation where G_ASSERT_ZEXT appears for AMDGPU is a copy from a physical register, which happens to use set the actual register class on the virtual register. After copy coalescing, the assert's source operand had a vreg with a set class. The verifier was strictly rejecting cases where the set class/bank weren't an exact match. Additionally, RegBankSelect was also expecting a register bank to be set on the register, not a class. This is much stricter than regular copies so relax this behavior. This now allows these 2 cases: 1. Source register has either class or bank, and the result does not 2. Source register has a register class, and the result is a register with a matching bank. This should avoid needing some kind of special handling to avoid violating this constraint when folding copies.		2022-04-22 10:49:50 -04:00
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generic-vreg-undef-use.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
live-ins-01.mir	…
live-ins-02.mir	…
live-ins-03.mir	…
test_copy.mir	…
test_copy_mismatch_types.mir	…
test_copy_physregs_x86.mir	[X86] AVX512FP16 instructions enabling 1/6	2021-08-10 12:46:01 +08:00
test_g_add.mir	…
test_g_addrspacecast.mir	…
test_g_assert_sext.mir	…
test_g_assert_sext_register_bank_class.mir	GlobalISel: Relax handling of G_ASSERT_* with source register classes	2022-04-22 10:49:50 -04:00
test_g_assert_zext.mir	…
test_g_assert_zext_register_bank_class.mir	GlobalISel: Relax handling of G_ASSERT_* with source register classes	2022-04-22 10:49:50 -04:00
test_g_bitcast.mir	…
test_g_brindirect_is_indirect_branch.mir	…
test_g_brjt.mir	…
test_g_brjt_is_indirect_branch.mir	…
test_g_build_vector.mir	…
test_g_build_vector_trunc.mir	…
test_g_bzero.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_concat_vectors.mir	…
test_g_constant.mir	…
test_g_dyn_stackalloc.mir	…
test_g_extract.mir	…
test_g_fcmp.mir	…
test_g_fconstant.mir	…
test_g_icmp.mir	…
test_g_insert.mir	…
test_g_intrinsic.mir	…
test_g_intrinsic_w_side_effects.mir	…
test_g_inttoptr.mir	…
test_g_jump_table.mir	…
test_g_llround.mir	[GlobalISel] Add G_LLROUND	2021-08-20 14:07:21 -07:00
test_g_load.mir	GlobalISel: Verify atomic load/store ordering restriction	2022-04-11 20:12:22 -04:00
test_g_lround.mir	[GlobalISel] Add G_LLROUND	2021-08-20 14:07:21 -07:00
test_g_memcpy.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_memcpy_inline.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memmove.mir	[GISel] Support llvm.memcpy.inline	2021-06-30 12:39:05 -07:00
test_g_memset.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_merge_values.mir	…
test_g_phi.mir	…
test_g_ptr_add.mir	…
test_g_ptrmask.mir	…
test_g_ptrtoint.mir	…
test_g_rotr_rotl.mir	[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR	2021-12-21 11:59:33 +00:00
test_g_select.mir	…
test_g_sext_inreg.mir	…
test_g_sextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_g_shift.mir	[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR	2021-12-21 11:59:33 +00:00
test_g_shuffle_vector.mir	…
test_g_store.mir	GlobalISel: Verify atomic load/store ordering restriction	2022-04-11 20:12:22 -04:00
test_g_trunc.mir	…
test_g_ubfx_sbfx.mir	Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mir	2021-03-24 11:23:08 -07:00
test_g_zextload.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
test_insert_subreg.mir	[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregs	2021-07-21 08:47:17 -07:00
test_phis_precede_nonphis.mir	…
test_vector_reductions.mir	[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalarization.	2021-08-19 16:38:52 -07:00
undef-should-only-be-set-on-subreg-defs.mir	MachineVerifier: Diagnose undef set on full register defs	2022-04-05 22:19:17 -04:00
verifier-generic-extend-truncate.mir	…
verifier-generic-types-1.mir	…
verifier-generic-types-2.mir	…
verifier-implicit-virtreg-invalid-physreg-liveness.mir	…
verifier-phi-fail0.mir	…
verifier-phi.mir	…
verifier-pseudo-terminators.mir	…
verifier-statepoint.mir	…
verify-regbankselected-dbg-undef-use.mir	[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.	2021-12-05 15:55:59 -05:00
verify-regbankselected.mir	…
verify-regops.mir	CodeGen: Print/parse LLTs in MachineMemOperands	2021-06-30 16:54:13 -04:00
verify-selected-dbg-undef-use.mir	[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.	2021-12-05 15:55:59 -05:00
verify-selected.mir	…