forked from OSchip/llvm-project
407b613d73
Integer materializing can generate LU12I_W, ORI, LU32I_D, LU52I_D and ADDI_W instructions. According to the sign-extended behavior of these instructions (except ORI), the generated instruction sequence can be improved. For example, load -1 into general register: The ADDI_W instruction performs the operation that the [31:0] bit data in the general register `rj` plus the 12-bit immediate `simm12` sign extension 32-bit data; the resultant [31:0] bit is sign extension, then written into the general register `rd`. Normal sequence: ``` lu12i.w $a0, -1 ori $a0, $a0, 2048 ``` Improved with sign-extended instruction: ``` addi.w $a0, $zero, -1 ``` Reviewed By: SixWeining, MaskRay Differential Revision: https://reviews.llvm.org/D123290 |
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| ir-instruction | ||
| 1ri.mir | ||
| 2r.mir | ||
| 2ri.mir | ||
| 3r.mir | ||
| 3ri.mir | ||
| imm.ll | ||
| lit.local.cfg | ||
| misc.mir | ||
| target_support.ll | ||