forked from OSchip/llvm-project
d16a631c12
This commit contains a refactoring that merges AVRRelaxMemOperations into AVRExpandPseudoInsts, so that we have a single place in code that expands the STDWPtrQRr opcode. Seizing the day, I've also fixed a couple of potential bugs with our previous implementation (e.g. when the destination register was killed, the previous implementation would try to .addDef() that killed register, crashing LLVM in the process - that's fixed now, as proved by the test). Reviewed By: benshi001 Differential Revision: https://reviews.llvm.org/D122533 |
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| .. | ||
| ADCWRdRr.mir | ||
| ADDWRdRr.mir | ||
| ANDIWRdK.mir | ||
| ANDWRdRr.mir | ||
| ASRBNRd.mir | ||
| ASRWNRd.mir | ||
| ASRWRd.mir | ||
| COMWRd.mir | ||
| CPCWRdRr.mir | ||
| CPWRdRr.mir | ||
| EORWRdRr.mir | ||
| FRMIDX.mir | ||
| INWRdA.mir | ||
| LDDWRdPtrQ.mir | ||
| LDDWRdYQ.mir | ||
| LDIWRdK.mir | ||
| LDSWRdK.mir | ||
| LDWRdPtr-same-src-dst.mir | ||
| LDWRdPtr.mir | ||
| LDWRdPtrPd.mir | ||
| LDWRdPtrPi.mir | ||
| LSLBNRd.mir | ||
| LSLWNRd.mir | ||
| LSLWRd.mir | ||
| LSRBNRd.mir | ||
| LSRWNRd.mir | ||
| LSRWRd.mir | ||
| NEGWRd.mir | ||
| ORIWRdK.mir | ||
| ORWRdRr.mir | ||
| OUTWARr.mir | ||
| POPWRd.mir | ||
| PUSHWRr.mir | ||
| SBCIWRdK.mir | ||
| SBCWRdRr.mir | ||
| SEXT.mir | ||
| STDWPtrQRr.mir | ||
| STSWKRr.mir | ||
| STWPtrPdRr.mir | ||
| STWPtrPiRr.mir | ||
| STWPtrRr.mir | ||
| SUBIWRdK.mir | ||
| SUBWRdRr.mir | ||
| ZEXT.mir | ||