forked from OSchip/llvm-project
40 lines
1.3 KiB
LLVM
40 lines
1.3 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs -amdgpu-s-branch-bits=6 < %s | FileCheck -check-prefix=GCN %s
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; Restrict maximum branch to between +31 and -32 dwords
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declare void @llvm.amdgcn.s.sleep(i32) #0
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@name1 = external addrspace(1) global i32
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@name2 = external addrspace(1) global i32
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@name3 = external addrspace(1) global i32
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; GCN-LABEL: {{^}}branch_offset_test:
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; GCN: s_cmp_eq_u32 s{{[0-9]+}}, 0
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; GCN-NEXT: s_cbranch_scc0 [[BB2:.LBB[0-9]+_[0-9]+]]
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; GCN-NEXT: .LBB{{[0-9]+}}_{{[0-9]+}}: ; %bb
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; GCN-NEXT: s_getpc_b64 s[[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]]
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; GCN-NEXT: [[POST_GETPC:.Lpost_getpc[0-9]+]]:{{$}}
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; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], ([[BB3:.LBB[0-9]+_[0-9]+]]-[[POST_GETPC]])&4294967295
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; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], ([[BB3]]-[[POST_GETPC]])>>32
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; GCN-NEXT: s_setpc_b64 s[[[PC_LO]]:[[PC_HI]]]
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; GCN-NEXT: [[BB2]]: ; %bb2
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; GCN-NEXT: s_getpc_b64 s[[[PC_LO]]:[[PC_HI]]]
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; GCN: [[BB3]]: ; %bb3
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define amdgpu_kernel void @branch_offset_test(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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bb:
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
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bb2:
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store i32 1, i32 addrspace(1)* @name1
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store i32 2, i32 addrspace(1)* @name2
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store i32 3, i32 addrspace(1)* @name3
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call void @llvm.amdgcn.s.sleep(i32 0)
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br label %bb3
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bb3:
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store volatile i32 %cnd, i32 addrspace(1)* %arg
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ret void
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}
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