forked from OSchip/llvm-project
90 lines
2.9 KiB
LLVM
90 lines
2.9 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
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; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX6,GFX678,ALL
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=SI,GFX8,GFX678,ALL
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; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,SI,ALL
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; ALL-LABEL: {{^}}build_vector2:
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
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; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
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define amdgpu_kernel void @build_vector2 (<2 x i32> addrspace(1)* %out) {
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entry:
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store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector4:
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; SI-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; SI-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; SI-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; SI-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
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; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
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define amdgpu_kernel void @build_vector4 (<4 x i32> addrspace(1)* %out) {
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entry:
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16:
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; R600: MOV
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; R600-NOT: MOV
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; GFX678: s_mov_b32 s3, 0xf000
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; GFX678: s_mov_b32 s2, -1
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; GFX678: v_mov_b32_e32 v0, 0x60005
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; GFX678: s_waitcnt lgkmcnt(0)
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; GFX678: buffer_store_dword v0, off, s[0:3], 0
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; GFX10: v_mov_b32_e32 v0, 0
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; GFX10: v_mov_b32_e32 v1, 0x60005
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; GFX10: s_waitcnt lgkmcnt(0)
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; GFX10: global_store_dword v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16 (<2 x i16> addrspace(1)* %out) {
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entry:
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store <2 x i16> <i16 5, i16 6>, <2 x i16> addrspace(1)* %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16_trunc:
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; R600: LSHR
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; R600: OR_INT
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; R600: LSHR
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; R600-NOT: MOV
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; GFX6: s_mov_b32 s3, 0xf000
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; GFX6: s_waitcnt lgkmcnt(0)
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; GFX6: s_lshr_b32 s2, s2, 16
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; GFX6: s_or_b32 s4, s2, 0x50000
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; GFX6: s_mov_b32 s2, -1
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; GFX6: v_mov_b32_e32 v0, s4
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; GFX6: buffer_store_dword v0, off, s[0:3], 0
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; GFX8: s_mov_b32 s3, 0xf000
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; GFX8: s_mov_b32 s2, -1
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; GFX8: s_waitcnt lgkmcnt(0)
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; GFX8: s_lshr_b32 s4, s4, 16
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; GFX8: s_or_b32 s4, s4, 0x50000
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; GFX8: v_mov_b32_e32 v0, s4
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; GFX8: buffer_store_dword v0, off, s[0:3], 0
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; GFX10: v_mov_b32_e32 v0, 0
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; GFX10: s_waitcnt lgkmcnt(0)
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; GFX10: s_lshr_b32 s2, s2, 16
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; GFX10: s_pack_ll_b32_b16 s2, s2, 5
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; GFX10: v_mov_b32_e32 v1, s2
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; GFX10: global_store_dword v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16_trunc (<2 x i16> addrspace(1)* %out, i32 %a) {
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%srl = lshr i32 %a, 16
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%trunc = trunc i32 %srl to i16
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%ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
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store <2 x i16> %ins.1, <2 x i16> addrspace(1)* %out
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ret void
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}
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