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llvm-project/llvm/test/MC/RISCV
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Craig Topper 210bc3dc0e [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1' 
vmsltu.vi v0, v1, 0 is always false there is no unsigned number
less than 0. vmsleu.vi v0, v1, -1 on the other hand is always true
since -1 will be considered unsigned max and all numbers are <=
unsigned max.

A similar problem exists for vmsgeu.vi v0, v1, 0 which is always true,
but becomes vmsgtu.vi v0, v1, -1 which is always false.

To match the GNU assembler we'll emit vmsne.vv and vmseq.vv with
the same register for these cases instead.

I'm using AsmParserOnly pseudo instructions here because we can't
match an explicit immediate in an InstAlias. And we can't use a
AsmOperand for the zero because the output we want doesn't use an
immediate so there's nowhere to name the AsmOperand we want to use.

To keep the implementations similar I'm also handling signed with
pseudo instructions even though they don't have this issue. This
way we can avoid the special renderMethod that decremented by 1 so
the immediate we see for the pseudo instruction in processInstruction
is 0 and not -1. Another option might have been to have a different
simm5_plus1 operand for the unsigned case or just live with the
immediate being pre-decremented. I felt this way was clearer, but I'm
open to other opinions.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D94035
 		2021-01-05 10:59:30 -08:00
..
rvv [RISCV] Don't parse 'vmsltu.vi v0, v1, 0' as 'vmsleu.vi v0, v1, -1' 2021-01-05 10:59:30 -08:00
align.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
attribute-arch.s [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
attribute-with-insts.s [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
attribute-with-option.s [RISCV] Support RISC-V ELF attributes sections in llvm-readobj. 2020-04-01 21:50:11 +08:00
attribute.s [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
cfi-regs-invalid.s
…
cfi-regs-valid.s
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cnop.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress-cjal.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
compress-debug-info.s [RISCV] Move DebugLoc Copy into CompressInstEmitter 2019-12-13 20:01:04 +00:00
compress-rv32b.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
compress-rv32d.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress-rv32f.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compress-rv32i.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
compress-rv64b.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
compress-rv64i.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
compressed-relocations.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
csr-aliases.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
data-directives-invalid.s
…
data-directives-valid.s
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debug-valid.s [RISCV] Add instruction definition for dret 2020-04-24 13:27:43 -07:00
elf-flags.s
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elf-header.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
empty-string.s
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fde-reloc.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
fixups-compressed.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
fixups-diagnostics.s
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fixups-expr.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
fixups-invalid.s [RISCV] Don't crash on unsupported relocations 2019-12-19 17:21:30 +00:00
fixups.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
function-call-invalid.s
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function-call.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
hilo-constaddr-expr.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
hilo-constaddr.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
invalid-attribute.s [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
invalid-instruction-spellcheck.s
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linker-relaxation.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
lit.local.cfg
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lla-invalid.s
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machine-csr-names-invalid.s
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machine-csr-names.s [RISCV] Enable the use of the old mucounteren name 2020-08-17 13:11:49 +01:00
mattr-invalid-combination.s Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
numeric-reg-names-d.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
numeric-reg-names-f.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
numeric-reg-names.s
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option-invalid.s
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option-mix.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
option-nopic.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
option-pic.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
option-pushpop.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
option-relax.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
option-rvc.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
pcrel-fixups.s [RISCV] Fix evaluating %pcrel_lo against global and weak symbols 2020-01-23 02:05:48 +00:00
pcrel-lo12-invalid.s [RISCV] Fix evaluating %pcrel_lo against global and weak symbols 2020-01-23 02:05:48 +00:00
priv-invalid.s
…
priv-valid.s
…
pseudo-jump-invalid.s [RISCV] Implement jump pseudo-instruction 2020-01-31 22:28:26 +00:00
pseudo-jump.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
reloc-directive-err.s [MC][RISCV] Make .reloc support arbitrary relocation types 2020-04-10 10:43:53 -07:00
reloc-directive.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
relocations.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
rv32-machine-csr-names.s
…
rv32-relaxation.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv32-user-csr-names.s
…
rv32a-invalid.s
…
rv32a-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32b-aliases-valid.s [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
rv32c-aliases-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32c-fuzzed-invalid.s
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rv32c-invalid.s [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive 2020-07-09 23:07:39 -07:00
rv32c-only-valid.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv32c-valid.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv32d-invalid.s
…
rv32d-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32dc-invalid.s
…
rv32dc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32e-invalid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rv32e-valid.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv32f-invalid.s [RISCV] Improve assembler missing feature warnings 2019-12-10 16:44:48 +00:00
rv32f-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32fc-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rv32fc-invalid.s
…
rv32fc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32i-aliases-invalid.s [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions 2020-12-10 19:25:51 +00:00
rv32i-aliases-valid.s [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
rv32i-invalid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rv32i-valid.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv32m-invalid.s [RISCV] Improve assembler missing feature warnings 2019-12-10 16:44:48 +00:00
rv32m-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbb-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbb-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbbp-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbbp-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbc-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbe-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbe-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbf-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbf-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbp-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbp-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbproposedc-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbproposedc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbr-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbr-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbs-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbs-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zbt-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv32zbt-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv32zfh-invalid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rv32zfh-valid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rv64-machine-csr-names.s
…
rv64-relax-all.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv64-relaxation.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rv64-user-csr-names.s
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rv64a-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rv64a-invalid.s
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rv64a-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64b-aliases-valid.s [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
rv64c-aliases-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64c-hints-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64c-invalid.s
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rv64c-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64d-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rv64d-invalid.s
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rv64d-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64dc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64f-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rv64f-invalid.s
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rv64f-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64i-aliases-invalid.s [RISCV] Improve assembler missing feature warnings 2019-12-10 16:44:48 +00:00
rv64i-aliases-valid.s [RISCV] Don't print zext.b alias. 2021-01-05 10:41:08 -08:00
rv64i-invalid.s
…
rv64i-pseudos.s
…
rv64i-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64m-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbb-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbb-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbbp-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbbp-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbc-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbe-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbe-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbf-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbf-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbm-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbm-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbp-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbp-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbproposedc-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbproposedc-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbr-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbr-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbs-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbs-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zbt-invalid.s [RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92) 2020-04-09 18:04:22 +01:00
rv64zbt-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rv64zfh-invalid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rv64zfh-valid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rva-aliases-invalid.s [RISCV] Check register class for AMO memory operands 2020-01-13 00:50:37 +00:00
rva-aliases-valid.s [RISCV] Fix unused check prefixes in test/MC/RISCV/ 2020-10-29 21:18:30 -07:00
rvc-aliases-valid.s
…
rvc-hints-invalid.s
…
rvc-hints-valid.s
…
rvd-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rvd-pseudos.s
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rvdc-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rvf-aliases-valid.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rvf-pseudos.s
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rvf-user-csr-names.s [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
rvi-aliases-valid.s [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump 2020-12-04 10:34:12 -08:00
rvi-alternate-abi-names.s
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rvi-pseudos-invalid.s [RISCVAsmParser] Allow a SymbolRef operand to be a complex expression 2020-12-01 16:08:09 -08:00
rvi-pseudos.s [RISCVAsmParser] Allow a SymbolRef operand to be a complex expression 2020-12-01 16:08:09 -08:00
rvv-user-csr-names.s [RISCV] Add MC tests for the User Vector CSRs 2020-11-16 10:40:18 -08:00
rvzfh-aliases-valid.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
rvzfh-pseudos.s [RISCV] Support Zfh half-precision floating-point extension. 2020-12-03 09:16:33 +08:00
supervisor-csr-names.s
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tail-call-invalid.s
…
tail-call.s [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
target-abi-invalid.s
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target-abi-valid.s
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user-csr-names-invalid.s
…
user-csr-names.s
…