forked from OSchip/llvm-project
62 lines
3.5 KiB
C
62 lines
3.5 KiB
C
// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED %s
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// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED %s
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// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,CONSTRAINED %s
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// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,CONSTRAINED %s
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// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM32 %s
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// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM64 %s
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// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM32 %s
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// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
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// RUN: -ffp-exception-behavior=strict \
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// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
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// RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM64 %s
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// REQUIRES: arm-registered-target,aarch64-registered-target
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#include <arm_neon.h>
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// COMMON-LABEL: test_vrndi_f32
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// COMMONIR: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
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// UNCONSTRAINED: [[VRNDI1_I:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %a)
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// CONSTRAINED: [[VRNDI1_I:%.*]] = call <2 x float> @llvm.experimental.constrained.nearbyint.v2f32(<2 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM64: frinti v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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// COMMONIR: ret <2 x float> [[VRNDI1_I]]
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float32x2_t test_vrndi_f32(float32x2_t a) {
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return vrndi_f32(a);
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}
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// COMMON-LABEL: test_vrndiq_f32
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// COMMONIR: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
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// UNCONSTRAINED: [[VRNDI1_I:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %a)
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// CONSTRAINED: [[VRNDI1_I:%.*]] = call <4 x float> @llvm.experimental.constrained.nearbyint.v4f32(<4 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict")
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM32: vrintr.f32 s{{[0-9]+}}, s{{[0-9]+}}
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// CHECK-ASM64: frinti v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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// COMMONIR: ret <4 x float> [[VRNDI1_I]]
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float32x4_t test_vrndiq_f32(float32x4_t a) {
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return vrndiq_f32(a);
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}
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