Rafael Espindola f44db24e1f Avoid explicit relocation sorting most of the time. ... These days relocations are created and stored in a deterministic way. The order they are created is also suitable for the .o file, so we don't need an explicit sort. The last remaining exception is MIPS. llvm-svn: 255902		2015-12-17 16:22:06 +00:00
..
AArch64	[AArch64] Fix FP16 vector instructions that should only accept low registers	2015-12-09 14:32:11 +00:00
AMDGPU	AMDGPU: Disallow flat_scr in SI assembler	2015-12-01 20:31:08 +00:00
ARM	Avoid explicit relocation sorting most of the time.	2015-12-17 16:22:06 +00:00
AsmParser	[MC] Use LShr for constant evaluation of ">>" on non-arm64 darwin.	2015-11-11 00:51:36 +00:00
COFF	MC: Simplify handling of temporary symbols in COFF writer.	2015-11-26 23:29:27 +00:00
Disassembler	Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"	2015-12-16 19:21:03 +00:00
ELF	[X86] Add relaxtion logic for SBB instructions.	2015-12-15 00:09:23 +00:00
Hexagon	[Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings.	2015-12-03 21:44:28 +00:00
MachO	[MC] Add a test for state reset in MCMachOStreamer	2015-12-05 01:02:53 +00:00
Markup	…
Mips	[mips][ias] Range check uimm10 operands	2015-12-09 13:48:05 +00:00
PowerPC	Relax a few more overspecified tests.	2015-11-03 19:38:19 +00:00
Sparc	Update test to take into account for r251271.	2015-10-26 03:34:29 +00:00
SystemZ	[SystemZ] Sort relocs to avoid code corruption by linker optimization	2015-12-16 18:12:40 +00:00
X86	I Added a triple flag for x86-evenDirective test.	2015-12-13 21:12:33 +00:00