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llvm-project/llvm/test/CodeGen
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Matt Arsenault 8ebbf25cb1 AMDGPU: Erase redundant redefs of m0 in SIFoldOperands 
Only handle simple inter-block redefs of m0 to the same value. This
avoids interference from redefs of m0 in SILoadStoreOptimzer. I was
initially teaching that pass to ignore redefs of m0, but having them
not exist beforehand is much simpler.

This is in preparation for deleting the current special m0 handling in
SIFixSGPRCopies to allow the register coalescer to handle the
difficult cases.

llvm-svn: 375449
 		2019-10-21 19:53:46 +00:00
..
AArch64 Reverted r375425 as it broke some buildbots. 2019-10-21 19:11:40 +00:00
AMDGPU AMDGPU: Erase redundant redefs of m0 in SIFoldOperands 2019-10-21 19:53:46 +00:00
ARC
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ARM [ARM] Extra qdadd patterns 2019-10-21 14:06:49 +00:00
AVR
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BPF [BPF] fix indirect call assembly code 2019-10-21 03:22:03 +00:00
Generic Reapply r374743 with a fix for the ocaml binding 2019-10-14 16:15:14 +00:00
Hexagon [DFAPacketizer] Use DFAEmitter. NFC. 2019-10-17 08:34:29 +00:00
Inputs
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Lanai [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
MIR [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
MSP430 [TargetLowering][DAGCombine][MSP430] add/use hook for Shift Amount Threshold (1/2) 2019-10-19 16:57:02 +00:00
Mips [MIPS GlobalISel] Add MSA registers to fprb. Select vector load, store 2019-10-15 09:30:08 +00:00
NVPTX [NVPTX] Restructure shfl instrinsics and add variants that return a predicate. 2019-10-14 16:53:34 +00:00
PowerPC [PowerPC] Regenerate test for D52431 2019-10-21 17:45:51 +00:00
RISCV [RISCV] Add MachineInstr immediate verification 2019-10-16 15:06:02 +00:00
SPARC
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SystemZ [FPEnv] Strict FP tests should use the requisite function attributes. 2019-10-04 17:03:46 +00:00
Thumb (Re)generate various tests. NFC 2019-10-08 16:16:26 +00:00
Thumb2 [ARM][MVE] Enable truncating masked stores 2019-10-17 12:11:18 +00:00
WebAssembly [WebAssembly] Allow multivalue signatures in object files 2019-10-18 20:27:30 +00:00
WinCFGuard
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WinEH [Windows] Replace TrapUnreachable with an int3 insertion pass 2019-09-09 23:04:25 +00:00
X86 [X86] Check Subtarget.hasSSE3() before calling shouldUseHorizontalOp and emitting X86ISD::FHADD in LowerUINT_TO_FP_i64. 2019-10-20 23:54:19 +00:00
XCore
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