forked from OSchip/llvm-project
846 lines
35 KiB
C++
846 lines
35 KiB
C++
//===- DAGISelMatcherGen.cpp - Matcher generator --------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "DAGISelMatcher.h"
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#include "CodeGenDAGPatterns.h"
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#include "Record.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringMap.h"
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#include <utility>
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using namespace llvm;
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/// getRegisterValueType - Look up and return the ValueType of the specified
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/// register. If the register is a member of multiple register classes which
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/// have different associated types, return MVT::Other.
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static MVT::SimpleValueType getRegisterValueType(Record *R,
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const CodeGenTarget &T) {
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bool FoundRC = false;
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MVT::SimpleValueType VT = MVT::Other;
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const std::vector<CodeGenRegisterClass> &RCs = T.getRegisterClasses();
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std::vector<Record*>::const_iterator Element;
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for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
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const CodeGenRegisterClass &RC = RCs[rc];
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if (!std::count(RC.Elements.begin(), RC.Elements.end(), R))
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continue;
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if (!FoundRC) {
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FoundRC = true;
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VT = RC.getValueTypeNum(0);
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continue;
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}
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// In multiple RC's. If the Types of the RC's do not agree, return
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// MVT::Other. The target is responsible for handling this.
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if (VT != RC.getValueTypeNum(0))
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// FIXME2: when does this happen? Abort?
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return MVT::Other;
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}
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return VT;
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}
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namespace {
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class MatcherGen {
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const PatternToMatch &Pattern;
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const CodeGenDAGPatterns &CGP;
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/// PatWithNoTypes - This is a clone of Pattern.getSrcPattern() that starts
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/// out with all of the types removed. This allows us to insert type checks
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/// as we scan the tree.
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TreePatternNode *PatWithNoTypes;
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/// VariableMap - A map from variable names ('$dst') to the recorded operand
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/// number that they were captured as. These are biased by 1 to make
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/// insertion easier.
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StringMap<unsigned> VariableMap;
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/// NextRecordedOperandNo - As we emit opcodes to record matched values in
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/// the RecordedNodes array, this keeps track of which slot will be next to
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/// record into.
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unsigned NextRecordedOperandNo;
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/// MatchedChainNodes - This maintains the position in the recorded nodes
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/// array of all of the recorded input nodes that have chains.
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SmallVector<unsigned, 2> MatchedChainNodes;
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/// PhysRegInputs - List list has an entry for each explicitly specified
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/// physreg input to the pattern. The first elt is the Register node, the
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/// second is the recorded slot number the input pattern match saved it in.
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SmallVector<std::pair<Record*, unsigned>, 2> PhysRegInputs;
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/// EmittedMergeInputChains - For nodes that match patterns involving
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/// chains, is set to true if we emitted the "MergeInputChains" operation.
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bool EmittedMergeInputChains;
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/// Matcher - This is the top level of the generated matcher, the result.
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MatcherNode *Matcher;
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/// CurPredicate - As we emit matcher nodes, this points to the latest check
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/// which should have future checks stuck into its Next position.
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MatcherNode *CurPredicate;
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public:
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MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
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~MatcherGen() {
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delete PatWithNoTypes;
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}
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void EmitMatcherCode();
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void EmitResultCode();
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MatcherNode *GetMatcher() const { return Matcher; }
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MatcherNode *GetCurPredicate() const { return CurPredicate; }
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private:
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void AddMatcherNode(MatcherNode *NewNode);
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void InferPossibleTypes();
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// Matcher Generation.
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void EmitMatchCode(const TreePatternNode *N, TreePatternNode *NodeNoTypes);
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void EmitLeafMatchCode(const TreePatternNode *N);
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void EmitOperatorMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes);
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// Result Code Generation.
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unsigned getNamedArgumentSlot(StringRef Name) {
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unsigned VarMapEntry = VariableMap[Name];
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assert(VarMapEntry != 0 &&
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"Variable referenced but not defined and not caught earlier!");
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return VarMapEntry-1;
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}
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/// GetInstPatternNode - Get the pattern for an instruction.
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const TreePatternNode *GetInstPatternNode(const DAGInstruction &Ins,
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const TreePatternNode *N);
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void EmitResultOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultOfNamedOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultLeafAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultInstructionAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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void EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
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SmallVectorImpl<unsigned> &ResultOps);
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};
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} // end anon namespace.
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MatcherGen::MatcherGen(const PatternToMatch &pattern,
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const CodeGenDAGPatterns &cgp)
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: Pattern(pattern), CGP(cgp), NextRecordedOperandNo(0),
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EmittedMergeInputChains(false), Matcher(0), CurPredicate(0) {
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// We need to produce the matcher tree for the patterns source pattern. To do
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// this we need to match the structure as well as the types. To do the type
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// matching, we want to figure out the fewest number of type checks we need to
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// emit. For example, if there is only one integer type supported by a
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// target, there should be no type comparisons at all for integer patterns!
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//
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// To figure out the fewest number of type checks needed, clone the pattern,
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// remove the types, then perform type inference on the pattern as a whole.
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// If there are unresolved types, emit an explicit check for those types,
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// apply the type to the tree, then rerun type inference. Iterate until all
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// types are resolved.
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//
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PatWithNoTypes = Pattern.getSrcPattern()->clone();
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PatWithNoTypes->RemoveAllTypes();
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// If there are types that are manifestly known, infer them.
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InferPossibleTypes();
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}
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/// InferPossibleTypes - As we emit the pattern, we end up generating type
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/// checks and applying them to the 'PatWithNoTypes' tree. As we do this, we
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/// want to propagate implied types as far throughout the tree as possible so
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/// that we avoid doing redundant type checks. This does the type propagation.
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void MatcherGen::InferPossibleTypes() {
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// TP - Get *SOME* tree pattern, we don't care which. It is only used for
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// diagnostics, which we know are impossible at this point.
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TreePattern &TP = *CGP.pf_begin()->second;
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try {
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bool MadeChange = true;
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while (MadeChange)
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MadeChange = PatWithNoTypes->ApplyTypeConstraints(TP,
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true/*Ignore reg constraints*/);
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} catch (...) {
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errs() << "Type constraint application shouldn't fail!";
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abort();
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}
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}
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/// AddMatcherNode - Add a matcher node to the current graph we're building.
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void MatcherGen::AddMatcherNode(MatcherNode *NewNode) {
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if (CurPredicate != 0)
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CurPredicate->setNext(NewNode);
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else
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Matcher = NewNode;
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CurPredicate = NewNode;
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}
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//===----------------------------------------------------------------------===//
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// Pattern Match Generation
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//===----------------------------------------------------------------------===//
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/// EmitLeafMatchCode - Generate matching code for leaf nodes.
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void MatcherGen::EmitLeafMatchCode(const TreePatternNode *N) {
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assert(N->isLeaf() && "Not a leaf?");
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// If there are node predicates for this node, generate their checks.
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for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
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AddMatcherNode(new CheckPredicateMatcherNode(N->getPredicateFns()[i]));
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// Direct match against an integer constant.
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if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue()))
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return AddMatcherNode(new CheckIntegerMatcherNode(II->getValue()));
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DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue());
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if (DI == 0) {
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errs() << "Unknown leaf kind: " << *DI << "\n";
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abort();
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}
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Record *LeafRec = DI->getDef();
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if (// Handle register references. Nothing to do here, they always match.
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LeafRec->isSubClassOf("RegisterClass") ||
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LeafRec->isSubClassOf("PointerLikeRegClass") ||
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// Place holder for SRCVALUE nodes. Nothing to do here.
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LeafRec->getName() == "srcvalue")
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return;
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// If we have a physreg reference like (mul gpr:$src, EAX) then we need to
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// record the register
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if (LeafRec->isSubClassOf("Register")) {
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AddMatcherNode(new RecordMatcherNode("physreg input "+LeafRec->getName()));
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PhysRegInputs.push_back(std::make_pair(LeafRec, NextRecordedOperandNo++));
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return;
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}
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if (LeafRec->isSubClassOf("ValueType"))
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return AddMatcherNode(new CheckValueTypeMatcherNode(LeafRec->getName()));
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if (LeafRec->isSubClassOf("CondCode"))
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return AddMatcherNode(new CheckCondCodeMatcherNode(LeafRec->getName()));
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if (LeafRec->isSubClassOf("ComplexPattern")) {
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// We can't model ComplexPattern uses that don't have their name taken yet.
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// The OPC_CheckComplexPattern operation implicitly records the results.
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if (N->getName().empty()) {
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errs() << "We expect complex pattern uses to have names: " << *N << "\n";
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exit(1);
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}
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// Handle complex pattern.
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const ComplexPattern &CP = CGP.getComplexPattern(LeafRec);
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// If we're at the root of the pattern, we have to check that the opcode
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// is a one of the ones requested to be matched.
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if (N == Pattern.getSrcPattern()) {
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const std::vector<Record*> &OpNodes = CP.getRootNodes();
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if (OpNodes.size() == 1) {
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StringRef OpName = CGP.getSDNodeInfo(OpNodes[0]).getEnumName();
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AddMatcherNode(new CheckOpcodeMatcherNode(OpName));
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} else if (!OpNodes.empty()) {
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SmallVector<StringRef, 4> OpNames;
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for (unsigned i = 0, e = OpNodes.size(); i != e; i++)
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OpNames.push_back(CGP.getSDNodeInfo(OpNodes[i]).getEnumName());
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AddMatcherNode(new CheckMultiOpcodeMatcherNode(OpNames.data(),
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OpNames.size()));
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}
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}
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// Emit a CheckComplexPat operation, which does the match (aborting if it
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// fails) and pushes the matched operands onto the recorded nodes list.
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AddMatcherNode(new CheckComplexPatMatcherNode(CP));
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// Record the right number of operands.
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NextRecordedOperandNo += CP.getNumOperands();
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if (CP.hasProperty(SDNPHasChain))
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++NextRecordedOperandNo; // Chained node operand.
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// If the complex pattern has a chain, then we need to keep track of the
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// fact that we just recorded a chain input. The chain input will be
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// matched as the last operand of the predicate if it was successful.
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if (CP.hasProperty(SDNPHasChain)) {
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// It is the last operand recorded.
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assert(NextRecordedOperandNo > 1 &&
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"Should have recorded input/result chains at least!");
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MatchedChainNodes.push_back(NextRecordedOperandNo-1);
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// If we need to check chains, do so, see comment for
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// "NodeHasProperty(SDNPHasChain" below.
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if (MatchedChainNodes.size() > 1) {
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// FIXME2: This is broken, we should eliminate this nonsense completely,
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// but we want to produce the same selections that the old matcher does
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// for now.
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unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2];
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AddMatcherNode(new CheckChainCompatibleMatcherNode(PrevOp));
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}
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}
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return;
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}
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errs() << "Unknown leaf kind: " << *N << "\n";
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abort();
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}
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void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes) {
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assert(!N->isLeaf() && "Not an operator?");
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const SDNodeInfo &CInfo = CGP.getSDNodeInfo(N->getOperator());
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// If this is an 'and R, 1234' where the operation is AND/OR and the RHS is
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// a constant without a predicate fn that has more that one bit set, handle
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// this as a special case. This is usually for targets that have special
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// handling of certain large constants (e.g. alpha with it's 8/16/32-bit
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// handling stuff). Using these instructions is often far more efficient
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// than materializing the constant. Unfortunately, both the instcombiner
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// and the dag combiner can often infer that bits are dead, and thus drop
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// them from the mask in the dag. For example, it might turn 'AND X, 255'
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// into 'AND X, 254' if it knows the low bit is set. Emit code that checks
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// to handle this.
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if ((N->getOperator()->getName() == "and" ||
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N->getOperator()->getName() == "or") &&
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N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateFns().empty() &&
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N->getPredicateFns().empty()) {
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if (IntInit *II = dynamic_cast<IntInit*>(N->getChild(1)->getLeafValue())) {
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if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
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if (N->getOperator()->getName() == "and")
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AddMatcherNode(new CheckAndImmMatcherNode(II->getValue()));
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else
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AddMatcherNode(new CheckOrImmMatcherNode(II->getValue()));
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// Match the LHS of the AND as appropriate.
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AddMatcherNode(new MoveChildMatcherNode(0));
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EmitMatchCode(N->getChild(0), NodeNoTypes->getChild(0));
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AddMatcherNode(new MoveParentMatcherNode());
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return;
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}
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}
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}
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// Check that the current opcode lines up.
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AddMatcherNode(new CheckOpcodeMatcherNode(CInfo.getEnumName()));
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// If there are node predicates for this node, generate their checks.
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for (unsigned i = 0, e = N->getPredicateFns().size(); i != e; ++i)
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AddMatcherNode(new CheckPredicateMatcherNode(N->getPredicateFns()[i]));
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// If this node has memory references (i.e. is a load or store), tell the
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// interpreter to capture them in the memref array.
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if (N->NodeHasProperty(SDNPMemOperand, CGP))
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AddMatcherNode(new RecordMemRefMatcherNode());
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// If this node has a chain, then the chain is operand #0 is the SDNode, and
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// the child numbers of the node are all offset by one.
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unsigned OpNo = 0;
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if (N->NodeHasProperty(SDNPHasChain, CGP)) {
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// Record the node and remember it in our chained nodes list.
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AddMatcherNode(new RecordMatcherNode("'" + N->getOperator()->getName() +
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"' chained node"));
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// Remember all of the input chains our pattern will match.
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MatchedChainNodes.push_back(NextRecordedOperandNo++);
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// If this is the second (e.g. indbr(load) or store(add(load))) or third
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// input chain (e.g. (store (add (load, load))) from msp430) we need to make
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// sure that folding the chain won't induce cycles in the DAG. This could
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// happen if there were an intermediate node between the indbr and load, for
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// example.
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if (MatchedChainNodes.size() > 1) {
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// FIXME2: This is broken, we should eliminate this nonsense completely,
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// but we want to produce the same selections that the old matcher does
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// for now.
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unsigned PrevOp = MatchedChainNodes[MatchedChainNodes.size()-2];
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AddMatcherNode(new CheckChainCompatibleMatcherNode(PrevOp));
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}
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// Don't look at the input chain when matching the tree pattern to the
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// SDNode.
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OpNo = 1;
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// If this node is not the root and the subtree underneath it produces a
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// chain, then the result of matching the node is also produce a chain.
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// Beyond that, this means that we're also folding (at least) the root node
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// into the node that produce the chain (for example, matching
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// "(add reg, (load ptr))" as a add_with_memory on X86). This is
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// problematic, if the 'reg' node also uses the load (say, its chain).
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// Graphically:
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//
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// [LD]
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// ^ ^
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// | \ DAG's like cheese.
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// / |
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// / [YY]
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// | ^
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// [XX]--/
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//
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// It would be invalid to fold XX and LD. In this case, folding the two
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// nodes together would induce a cycle in the DAG, making it a 'cyclic DAG'
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// To prevent this, we emit a dynamic check for legality before allowing
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// this to be folded.
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//
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const TreePatternNode *Root = Pattern.getSrcPattern();
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if (N != Root) { // Not the root of the pattern.
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// If there is a node between the root and this node, then we definitely
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// need to emit the check.
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bool NeedCheck = !Root->hasChild(N);
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// If it *is* an immediate child of the root, we can still need a check if
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// the root SDNode has multiple inputs. For us, this means that it is an
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// intrinsic, has multiple operands, or has other inputs like chain or
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// flag).
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if (!NeedCheck) {
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const SDNodeInfo &PInfo = CGP.getSDNodeInfo(Root->getOperator());
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NeedCheck =
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Root->getOperator() == CGP.get_intrinsic_void_sdnode() ||
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Root->getOperator() == CGP.get_intrinsic_w_chain_sdnode() ||
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Root->getOperator() == CGP.get_intrinsic_wo_chain_sdnode() ||
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PInfo.getNumOperands() > 1 ||
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PInfo.hasProperty(SDNPHasChain) ||
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PInfo.hasProperty(SDNPInFlag) ||
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PInfo.hasProperty(SDNPOptInFlag);
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}
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if (NeedCheck)
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AddMatcherNode(new CheckFoldableChainNodeMatcherNode());
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}
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}
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// If this node is known to have an input flag or if it *might* have an input
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// flag, capture it as the flag input of the pattern.
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if (N->NodeHasProperty(SDNPOptInFlag, CGP) ||
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N->NodeHasProperty(SDNPInFlag, CGP))
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AddMatcherNode(new CaptureFlagInputMatcherNode());
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for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i, ++OpNo) {
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// Get the code suitable for matching this child. Move to the child, check
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// it then move back to the parent.
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AddMatcherNode(new MoveChildMatcherNode(OpNo));
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EmitMatchCode(N->getChild(i), NodeNoTypes->getChild(i));
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AddMatcherNode(new MoveParentMatcherNode());
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}
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}
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void MatcherGen::EmitMatchCode(const TreePatternNode *N,
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TreePatternNode *NodeNoTypes) {
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// If N and NodeNoTypes don't agree on a type, then this is a case where we
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// need to do a type check. Emit the check, apply the tyep to NodeNoTypes and
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// reinfer any correlated types.
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if (NodeNoTypes->getExtTypes() != N->getExtTypes()) {
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AddMatcherNode(new CheckTypeMatcherNode(N->getTypeNum(0)));
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NodeNoTypes->setTypes(N->getExtTypes());
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InferPossibleTypes();
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}
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// If this node has a name associated with it, capture it in VariableMap. If
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// we already saw this in the pattern, emit code to verify dagness.
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if (!N->getName().empty()) {
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unsigned &VarMapEntry = VariableMap[N->getName()];
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if (VarMapEntry == 0) {
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// If it is a named node, we must emit a 'Record' opcode.
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VarMapEntry = ++NextRecordedOperandNo;
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AddMatcherNode(new RecordMatcherNode("$" + N->getName()));
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} else {
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// If we get here, this is a second reference to a specific name. Since
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// we already have checked that the first reference is valid, we don't
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// have to recursively match it, just check that it's the same as the
|
|
// previously named thing.
|
|
AddMatcherNode(new CheckSameMatcherNode(VarMapEntry-1));
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (N->isLeaf())
|
|
EmitLeafMatchCode(N);
|
|
else
|
|
EmitOperatorMatchCode(N, NodeNoTypes);
|
|
}
|
|
|
|
void MatcherGen::EmitMatcherCode() {
|
|
// If the pattern has a predicate on it (e.g. only enabled when a subtarget
|
|
// feature is around, do the check).
|
|
if (!Pattern.getPredicateCheck().empty())
|
|
AddMatcherNode(new
|
|
CheckPatternPredicateMatcherNode(Pattern.getPredicateCheck()));
|
|
|
|
// Emit the matcher for the pattern structure and types.
|
|
EmitMatchCode(Pattern.getSrcPattern(), PatWithNoTypes);
|
|
}
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Node Result Generation
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void MatcherGen::EmitResultOfNamedOperand(const TreePatternNode *N,
|
|
SmallVectorImpl<unsigned> &ResultOps){
|
|
assert(!N->getName().empty() && "Operand not named!");
|
|
|
|
unsigned SlotNo = getNamedArgumentSlot(N->getName());
|
|
|
|
// A reference to a complex pattern gets all of the results of the complex
|
|
// pattern's match.
|
|
if (const ComplexPattern *CP = N->getComplexPatternInfo(CGP)) {
|
|
// The first slot entry is the node itself, the subsequent entries are the
|
|
// matched values.
|
|
for (unsigned i = 0, e = CP->getNumOperands(); i != e; ++i)
|
|
ResultOps.push_back(SlotNo+i+1);
|
|
return;
|
|
}
|
|
|
|
// If this is an 'imm' or 'fpimm' node, make sure to convert it to the target
|
|
// version of the immediate so that it doesn't get selected due to some other
|
|
// node use.
|
|
if (!N->isLeaf()) {
|
|
StringRef OperatorName = N->getOperator()->getName();
|
|
if (OperatorName == "imm" || OperatorName == "fpimm") {
|
|
AddMatcherNode(new EmitConvertToTargetMatcherNode(SlotNo));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
return;
|
|
}
|
|
}
|
|
|
|
ResultOps.push_back(SlotNo);
|
|
}
|
|
|
|
void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
|
|
SmallVectorImpl<unsigned> &ResultOps) {
|
|
assert(N->isLeaf() && "Must be a leaf");
|
|
|
|
if (IntInit *II = dynamic_cast<IntInit*>(N->getLeafValue())) {
|
|
AddMatcherNode(new EmitIntegerMatcherNode(II->getValue(),N->getTypeNum(0)));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
return;
|
|
}
|
|
|
|
// If this is an explicit register reference, handle it.
|
|
if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
|
|
if (DI->getDef()->isSubClassOf("Register")) {
|
|
AddMatcherNode(new EmitRegisterMatcherNode(DI->getDef(),
|
|
N->getTypeNum(0)));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
return;
|
|
}
|
|
|
|
if (DI->getDef()->getName() == "zero_reg") {
|
|
AddMatcherNode(new EmitRegisterMatcherNode(0, N->getTypeNum(0)));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
return;
|
|
}
|
|
|
|
// Handle a reference to a register class. This is used
|
|
// in COPY_TO_SUBREG instructions.
|
|
if (DI->getDef()->isSubClassOf("RegisterClass")) {
|
|
std::string Value = getQualifiedName(DI->getDef()) + "RegClassID";
|
|
AddMatcherNode(new EmitStringIntegerMatcherNode(Value, MVT::i32));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
return;
|
|
}
|
|
}
|
|
|
|
errs() << "unhandled leaf node: \n";
|
|
N->dump();
|
|
}
|
|
|
|
/// GetInstPatternNode - Get the pattern for an instruction.
|
|
///
|
|
const TreePatternNode *MatcherGen::
|
|
GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
|
|
const TreePattern *InstPat = Inst.getPattern();
|
|
|
|
// FIXME2?: Assume actual pattern comes before "implicit".
|
|
TreePatternNode *InstPatNode;
|
|
if (InstPat)
|
|
InstPatNode = InstPat->getTree(0);
|
|
else if (/*isRoot*/ N == Pattern.getDstPattern())
|
|
InstPatNode = Pattern.getSrcPattern();
|
|
else
|
|
return 0;
|
|
|
|
if (InstPatNode && !InstPatNode->isLeaf() &&
|
|
InstPatNode->getOperator()->getName() == "set")
|
|
InstPatNode = InstPatNode->getChild(InstPatNode->getNumChildren()-1);
|
|
|
|
return InstPatNode;
|
|
}
|
|
|
|
void MatcherGen::
|
|
EmitResultInstructionAsOperand(const TreePatternNode *N,
|
|
SmallVectorImpl<unsigned> &OutputOps) {
|
|
Record *Op = N->getOperator();
|
|
const CodeGenTarget &CGT = CGP.getTargetInfo();
|
|
CodeGenInstruction &II = CGT.getInstruction(Op->getName());
|
|
const DAGInstruction &Inst = CGP.getInstruction(Op);
|
|
|
|
// If we can, get the pattern for the instruction we're generating. We derive
|
|
// a variety of information from this pattern, such as whether it has a chain.
|
|
//
|
|
// FIXME2: This is extremely dubious for several reasons, not the least of
|
|
// which it gives special status to instructions with patterns that Pat<>
|
|
// nodes can't duplicate.
|
|
const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
|
|
|
|
// NodeHasChain - Whether the instruction node we're creating takes chains.
|
|
bool NodeHasChain = InstPatNode &&
|
|
InstPatNode->TreeHasProperty(SDNPHasChain, CGP);
|
|
|
|
bool isRoot = N == Pattern.getDstPattern();
|
|
|
|
// NodeHasOutFlag - True if this node has a flag.
|
|
bool NodeHasInFlag = false, NodeHasOutFlag = false;
|
|
if (isRoot) {
|
|
const TreePatternNode *SrcPat = Pattern.getSrcPattern();
|
|
NodeHasInFlag = SrcPat->TreeHasProperty(SDNPOptInFlag, CGP) ||
|
|
SrcPat->TreeHasProperty(SDNPInFlag, CGP);
|
|
|
|
// FIXME2: this is checking the entire pattern, not just the node in
|
|
// question, doing this just for the root seems like a total hack.
|
|
NodeHasOutFlag = SrcPat->TreeHasProperty(SDNPOutFlag, CGP);
|
|
}
|
|
|
|
// NumResults - This is the number of results produced by the instruction in
|
|
// the "outs" list.
|
|
unsigned NumResults = Inst.getNumResults();
|
|
|
|
// Loop over all of the operands of the instruction pattern, emitting code
|
|
// to fill them all in. The node 'N' usually has number children equal to
|
|
// the number of input operands of the instruction. However, in cases
|
|
// where there are predicate operands for an instruction, we need to fill
|
|
// in the 'execute always' values. Match up the node operands to the
|
|
// instruction operands to do this.
|
|
SmallVector<unsigned, 8> InstOps;
|
|
for (unsigned ChildNo = 0, InstOpNo = NumResults, e = II.OperandList.size();
|
|
InstOpNo != e; ++InstOpNo) {
|
|
|
|
// Determine what to emit for this operand.
|
|
Record *OperandNode = II.OperandList[InstOpNo].Rec;
|
|
if ((OperandNode->isSubClassOf("PredicateOperand") ||
|
|
OperandNode->isSubClassOf("OptionalDefOperand")) &&
|
|
!CGP.getDefaultOperand(OperandNode).DefaultOps.empty()) {
|
|
// This is a predicate or optional def operand; emit the
|
|
// 'default ops' operands.
|
|
const DAGDefaultOperand &DefaultOp =
|
|
CGP.getDefaultOperand(II.OperandList[InstOpNo].Rec);
|
|
for (unsigned i = 0, e = DefaultOp.DefaultOps.size(); i != e; ++i)
|
|
EmitResultOperand(DefaultOp.DefaultOps[i], InstOps);
|
|
continue;
|
|
}
|
|
|
|
// Otherwise this is a normal operand or a predicate operand without
|
|
// 'execute always'; emit it.
|
|
EmitResultOperand(N->getChild(ChildNo), InstOps);
|
|
++ChildNo;
|
|
}
|
|
|
|
// Nodes that match patterns with (potentially multiple) chain inputs have to
|
|
// merge them together into a token factor.
|
|
if (NodeHasChain && !EmittedMergeInputChains) {
|
|
// FIXME2: Move this out of emitresult to a top level place.
|
|
assert(!MatchedChainNodes.empty() &&
|
|
"How can this node have chain if no inputs do?");
|
|
// Otherwise, we have to emit an operation to merge the input chains and
|
|
// set this as the current input chain.
|
|
AddMatcherNode(new EmitMergeInputChainsMatcherNode
|
|
(MatchedChainNodes.data(), MatchedChainNodes.size()));
|
|
EmittedMergeInputChains = true;
|
|
}
|
|
|
|
// If this node has an input flag or explicitly specified input physregs, we
|
|
// need to add chained and flagged copyfromreg nodes and materialize the flag
|
|
// input.
|
|
if (isRoot && !PhysRegInputs.empty()) {
|
|
// Emit all of the CopyToReg nodes for the input physical registers. These
|
|
// occur in patterns like (mul:i8 AL:i8, GR8:i8:$src).
|
|
for (unsigned i = 0, e = PhysRegInputs.size(); i != e; ++i)
|
|
AddMatcherNode(new EmitCopyToRegMatcherNode(PhysRegInputs[i].second,
|
|
PhysRegInputs[i].first));
|
|
// Even if the node has no other flag inputs, the resultant node must be
|
|
// flagged to the CopyFromReg nodes we just generated.
|
|
NodeHasInFlag = true;
|
|
}
|
|
|
|
// Result order: node results, chain, flags
|
|
|
|
// Determine the result types.
|
|
SmallVector<MVT::SimpleValueType, 4> ResultVTs;
|
|
if (NumResults != 0 && N->getTypeNum(0) != MVT::isVoid) {
|
|
// FIXME2: If the node has multiple results, we should add them. For now,
|
|
// preserve existing behavior?!
|
|
ResultVTs.push_back(N->getTypeNum(0));
|
|
}
|
|
|
|
|
|
// If this is the root instruction of a pattern that has physical registers in
|
|
// its result pattern, add output VTs for them. For example, X86 has:
|
|
// (set AL, (mul ...))
|
|
// This also handles implicit results like:
|
|
// (implicit EFLAGS)
|
|
if (isRoot && Pattern.getDstRegs().size() != 0) {
|
|
for (unsigned i = 0; i != Pattern.getDstRegs().size(); ++i)
|
|
if (Pattern.getDstRegs()[i]->isSubClassOf("Register"))
|
|
ResultVTs.push_back(getRegisterValueType(Pattern.getDstRegs()[i], CGT));
|
|
}
|
|
if (NodeHasChain)
|
|
ResultVTs.push_back(MVT::Other);
|
|
if (NodeHasOutFlag)
|
|
ResultVTs.push_back(MVT::Flag);
|
|
|
|
// FIXME2: Instead of using the isVariadic flag on the instruction, we should
|
|
// have an SDNP that indicates variadicism. The TargetInstrInfo isVariadic
|
|
// property should be inferred from this when an instruction has a pattern.
|
|
int NumFixedArityOperands = -1;
|
|
if (isRoot && II.isVariadic)
|
|
NumFixedArityOperands = Pattern.getSrcPattern()->getNumChildren();
|
|
|
|
// If this is the root node and any of the nodes matched nodes in the input
|
|
// pattern have MemRefs in them, have the interpreter collect them and plop
|
|
// them onto this node.
|
|
//
|
|
// FIXME3: This is actively incorrect for result patterns where the root of
|
|
// the pattern is not the memory reference and is also incorrect when the
|
|
// result pattern has multiple memory-referencing instructions. For example,
|
|
// in the X86 backend, this pattern causes the memrefs to get attached to the
|
|
// CVTSS2SDrr instead of the MOVSSrm:
|
|
//
|
|
// def : Pat<(extloadf32 addr:$src),
|
|
// (CVTSS2SDrr (MOVSSrm addr:$src))>;
|
|
//
|
|
bool NodeHasMemRefs =
|
|
isRoot && Pattern.getSrcPattern()->TreeHasProperty(SDNPMemOperand, CGP);
|
|
|
|
// FIXME: Eventually add a SelectNodeTo form. It works if the new node has a
|
|
// superset of the results of the old node, in the same places. E.g. turning
|
|
// (add (load)) -> add32rm is ok because result #0 is the result and result #1
|
|
// is new.
|
|
AddMatcherNode(new EmitNodeMatcherNode(II.Namespace+"::"+II.TheDef->getName(),
|
|
ResultVTs.data(), ResultVTs.size(),
|
|
InstOps.data(), InstOps.size(),
|
|
NodeHasChain, NodeHasInFlag,
|
|
NodeHasMemRefs,NumFixedArityOperands));
|
|
|
|
// The non-chain and non-flag results of the newly emitted node get recorded.
|
|
for (unsigned i = 0, e = ResultVTs.size(); i != e; ++i) {
|
|
if (ResultVTs[i] == MVT::Other || ResultVTs[i] == MVT::Flag) break;
|
|
OutputOps.push_back(NextRecordedOperandNo++);
|
|
}
|
|
|
|
// FIXME2: Kill off all the SelectionDAG::SelectNodeTo and getMachineNode
|
|
// variants. Call MorphNodeTo instead of SelectNodeTo.
|
|
}
|
|
|
|
void MatcherGen::
|
|
EmitResultSDNodeXFormAsOperand(const TreePatternNode *N,
|
|
SmallVectorImpl<unsigned> &ResultOps) {
|
|
assert(N->getOperator()->isSubClassOf("SDNodeXForm") && "Not SDNodeXForm?");
|
|
|
|
// Emit the operand.
|
|
SmallVector<unsigned, 8> InputOps;
|
|
|
|
// FIXME2: Could easily generalize this to support multiple inputs and outputs
|
|
// to the SDNodeXForm. For now we just support one input and one output like
|
|
// the old instruction selector.
|
|
assert(N->getNumChildren() == 1);
|
|
EmitResultOperand(N->getChild(0), InputOps);
|
|
|
|
// The input currently must have produced exactly one result.
|
|
assert(InputOps.size() == 1 && "Unexpected input to SDNodeXForm");
|
|
|
|
AddMatcherNode(new EmitNodeXFormMatcherNode(InputOps[0], N->getOperator()));
|
|
ResultOps.push_back(NextRecordedOperandNo++);
|
|
}
|
|
|
|
void MatcherGen::EmitResultOperand(const TreePatternNode *N,
|
|
SmallVectorImpl<unsigned> &ResultOps) {
|
|
// This is something selected from the pattern we matched.
|
|
if (!N->getName().empty())
|
|
return EmitResultOfNamedOperand(N, ResultOps);
|
|
|
|
if (N->isLeaf())
|
|
return EmitResultLeafAsOperand(N, ResultOps);
|
|
|
|
Record *OpRec = N->getOperator();
|
|
if (OpRec->isSubClassOf("Instruction"))
|
|
return EmitResultInstructionAsOperand(N, ResultOps);
|
|
if (OpRec->isSubClassOf("SDNodeXForm"))
|
|
return EmitResultSDNodeXFormAsOperand(N, ResultOps);
|
|
errs() << "Unknown result node to emit code for: " << *N << '\n';
|
|
throw std::string("Unknown node in result pattern!");
|
|
}
|
|
|
|
void MatcherGen::EmitResultCode() {
|
|
// Codegen the root of the result pattern, capturing the resulting values.
|
|
SmallVector<unsigned, 8> Ops;
|
|
EmitResultOperand(Pattern.getDstPattern(), Ops);
|
|
|
|
// At this point, we have however many values the result pattern produces.
|
|
// However, the input pattern might not need all of these. If there are
|
|
// excess values at the end (such as condition codes etc) just lop them off.
|
|
// This doesn't need to worry about flags or chains, just explicit results.
|
|
//
|
|
// FIXME2: This doesn't work because there is currently no way to get an
|
|
// accurate count of the # results the source pattern sets. This is because
|
|
// of the "parallel" construct in X86 land, which looks like this:
|
|
//
|
|
//def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
|
|
// (implicit EFLAGS)),
|
|
// (AND8rr GR8:$src1, GR8:$src2)>;
|
|
//
|
|
// This idiom means to match the two-result node X86and_flag (which is
|
|
// declared as returning a single result, because we can't match multi-result
|
|
// nodes yet). In this case, we would have to know that the input has two
|
|
// results. However, mul8r is modelled exactly the same way, but without
|
|
// implicit defs included. The fix is to support multiple results directly
|
|
// and eliminate 'parallel'.
|
|
//
|
|
// FIXME2: When this is fixed, we should revert the terrible hack in the
|
|
// OPC_EmitNode code in the interpreter.
|
|
#if 0
|
|
const TreePatternNode *Src = Pattern.getSrcPattern();
|
|
unsigned NumSrcResults = Src->getTypeNum(0) != MVT::isVoid ? 1 : 0;
|
|
NumSrcResults += Pattern.getDstRegs().size();
|
|
assert(Ops.size() >= NumSrcResults && "Didn't provide enough results");
|
|
Ops.resize(NumSrcResults);
|
|
#endif
|
|
|
|
// We know that the resulting pattern has exactly one result/
|
|
// FIXME2: why? what about something like (set a,b,c, (complexpat))
|
|
// FIXME2: Implicit results should be pushed here I guess?
|
|
AddMatcherNode(new CompleteMatchMatcherNode(Ops.data(), Ops.size(), Pattern));
|
|
}
|
|
|
|
|
|
MatcherNode *llvm::ConvertPatternToMatcher(const PatternToMatch &Pattern,
|
|
const CodeGenDAGPatterns &CGP) {
|
|
MatcherGen Gen(Pattern, CGP);
|
|
|
|
// Generate the code for the matcher.
|
|
Gen.EmitMatcherCode();
|
|
|
|
|
|
// FIXME2: Kill extra MoveParent commands at the end of the matcher sequence.
|
|
// FIXME2: Split result code out to another table, and make the matcher end
|
|
// with an "Emit <index>" command. This allows result generation stuff to be
|
|
// shared and factored?
|
|
|
|
// If the match succeeds, then we generate Pattern.
|
|
Gen.EmitResultCode();
|
|
|
|
// Unconditional match.
|
|
return Gen.GetMatcher();
|
|
}
|
|
|
|
|
|
|