forked from OSchip/llvm-project
159 lines
4.6 KiB
YAML
159 lines
4.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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--- |
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; ModuleID = 'sitofp_legal.ll'
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source_filename = "sitofp.c"
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Function Attrs: norecurse nounwind readnone uwtable
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define dso_local float @int32_to_float(i32 %a) local_unnamed_addr #0 {
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entry:
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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; Function Attrs: norecurse nounwind readnone uwtable
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define dso_local float @int64_to_float(i64 %a) local_unnamed_addr #0 {
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entry:
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%conv = sitofp i64 %a to float
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ret float %conv
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}
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; Function Attrs: norecurse nounwind readnone uwtable
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define dso_local double @int32_to_double(i32 %a) local_unnamed_addr #0 {
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entry:
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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; Function Attrs: norecurse nounwind readnone uwtable
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define dso_local double @int64_to_double(i64 %a) local_unnamed_addr #0 {
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entry:
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%conv = sitofp i64 %a to double
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ret double %conv
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}
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attributes #0 = { norecurse nounwind readnone uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!llvm.module.flags = !{!0}
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!llvm.ident = !{!1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!"clang version 7.0.0"}
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...
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---
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name: int32_to_float
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1.entry:
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liveins: $edi
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; CHECK-LABEL: name: int32_to_float
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[CVTSI2SSrr:%[0-9]+]]:fr32 = CVTSI2SSrr [[COPY]]
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; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SSrr]]
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; CHECK: $xmm0 = COPY [[COPY1]]
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; CHECK: RET 0, implicit $xmm0
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%0:gpr(s32) = COPY $edi
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%1:vecr(s32) = G_SITOFP %0(s32)
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%2:vecr(s128) = G_ANYEXT %1(s32)
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$xmm0 = COPY %2(s128)
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RET 0, implicit $xmm0
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...
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---
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name: int64_to_float
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1.entry:
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liveins: $rdi
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; CHECK-LABEL: name: int64_to_float
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; CHECK: liveins: $rdi
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[CVTSI642SSrr:%[0-9]+]]:fr32 = CVTSI642SSrr [[COPY]]
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; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SSrr]]
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; CHECK: $xmm0 = COPY [[COPY1]]
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; CHECK: RET 0, implicit $xmm0
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%0:gpr(s64) = COPY $rdi
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%1:vecr(s32) = G_SITOFP %0(s64)
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%2:vecr(s128) = G_ANYEXT %1(s32)
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$xmm0 = COPY %2(s128)
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RET 0, implicit $xmm0
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...
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---
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name: int32_to_double
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1.entry:
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liveins: $edi
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; CHECK-LABEL: name: int32_to_double
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; CHECK: liveins: $edi
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; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
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; CHECK: [[CVTSI2SDrr:%[0-9]+]]:fr64 = CVTSI2SDrr [[COPY]]
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; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI2SDrr]]
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; CHECK: $xmm0 = COPY [[COPY1]]
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; CHECK: RET 0, implicit $xmm0
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%0:gpr(s32) = COPY $edi
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%1:vecr(s64) = G_SITOFP %0(s32)
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%2:vecr(s128) = G_ANYEXT %1(s64)
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$xmm0 = COPY %2(s128)
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RET 0, implicit $xmm0
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...
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---
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name: int64_to_double
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr }
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- { id: 1, class: vecr }
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- { id: 2, class: vecr }
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body: |
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bb.1.entry:
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liveins: $rdi
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; CHECK-LABEL: name: int64_to_double
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; CHECK: liveins: $rdi
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; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
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; CHECK: [[CVTSI642SDrr:%[0-9]+]]:fr64 = CVTSI642SDrr [[COPY]]
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; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY [[CVTSI642SDrr]]
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; CHECK: $xmm0 = COPY [[COPY1]]
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; CHECK: RET 0, implicit $xmm0
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%0:gpr(s64) = COPY $rdi
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%1:vecr(s64) = G_SITOFP %0(s64)
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%2:vecr(s128) = G_ANYEXT %1(s64)
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$xmm0 = COPY %2(s128)
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RET 0, implicit $xmm0
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...
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