llvm-project/llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-cl...

14 lines
341 B
YAML

# RUN: not llc -march=amdgcn -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
# CHECK: :8:45: incorrect register class for field
# CHECK: scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'
---
name: wrong_reg_class_scratch_rsrc_reg
machineFunctionInfo:
scratchRSrcReg: '$vgpr0_vgpr1_vgpr2_vgpr3'
body: |
bb.0:
S_ENDPGM
...